Mainboard PX915-SLI
23
Advanced Chipset Features
DRAM Timing Selectable
This option determines DRAM clock/ timing using SPD or manual configuration.
Make sure your memory module has SPD (Serial Presence Data), if you want to select the
“By SPD” option.
Options: Manual,By SPD (default)
CAS Latency Time
This option determines CAS Latency. When synchronous DRAM is installed, the number of
clock cycles of CAS latency depends on the DRAM timing. Do not reset this option from
the default value specified by the system engineer. This option is adjustable only when
“DRAM Timing Selectable” is set to “Manual”. This option is locked when “DRAM Timing
Selectable” is set to “By SPD” and is automatically determined by the system.
Options: 2,2.5,3
DRAM RAS# to CAS# Delay
This option allows you to select a delay time between the CAS and RAS strobe signals. It
only applies when DRAM is written to, read from, or refreshed. This option is adjustable
only when “DRAM Timing Selectable” is set to “manual”. This option is locked when “DRAM
Timing Selectable” is set to “By SPD” and is automatically determined by the system.
Options: 4,3,2
DRAM RAS# Precharge
This option allows you to select the DRAM RAS# precharged time. The ROW address strobe
must be precharged again before DRAM is refreshed. An inadequate configuration may
result in incomplete data. This option is adjustable only when “DRAM Timing Selectable” is
set to “manual”. This option is locked when “DRAM Timing Selectable” is set to “By SPD”
and is automatically determined by the system.
Options: 4,3,2
Precharge Delay
This option allows you to select DRAM Active to Precharge Delay. This option is locked
when “DRAM Timing Selectable” is set to “By SPD” and is automatically determined by the
system.
Options: 8,7,6,5
System BIOS Cacheable
When enabled, accesses to system BIOS ROM addressed at F0000H-FFFFFH are cached,
provided that the cache controller is enabled. Options: Enabled (default), Disabled
