KM400T-8X Series
28
AGP Master 1 WS Write
d with one wait state.
led
uted with one wait state.
Options: Disabled (default)
、
Enabled
ll the 8X VGA card. Options: Enabled (default)
、
Disabled
C
with zero-wait states.
ptions: Enabled (default)
、
Disabled
delay transactions cycles. Select
ifications. Options: Disabled
、
Enabled (default)
M
W
adapter ROM. When this area is
r
are installing for
m
System BIOS Cacheable
W
H are cached, provided
t
V
Select “Enabled” to allow caching of the video RAM which may improve performance. If any other
p
area, a system error may result. Options: Enabled
、
Disabled (default)
When enabled, writes to the AGP (Accelerated Graphics Port) are execute
Options: Disabled (default)
、
Enab
AGP Master 1 WS Read
When enabled, reads from AGP (Accelerated Graphics Port) are exec
AGP3.0 Calibration cycle
This item will appear when you insta
PU & PCI Bus Control
ress <Enter> to enter the next page for CPU & PCI Bus Control
P
PCI 1/2 Master 0 WS Write
bu
When enabled, writes to the PCI
s are executed
O
PCI Delay Transaction
The chipset has an embedded 32-bit post write buffer to support
Enabled to comply with PCI spec
emory Hole
hen enabled, you can reserve an area of system memory for ISA
eserved, it cannot be cached. Refer to the user documentation of the peripheral you
ore information. Options: Disabled (default)
、
15M-16M
hen enabled, accesses to system BIOS ROM addressed at F0000H-FFFFF
hat the cache controller is enabled. Options: Enabled
、
Disabled (default)
ideo RAM Cacheable
rogram writes to this memory
