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ATS9360 User Manual
Fast External Clock
This setting must be used when the external clock frequency
is in the range of 1.8 GHz down to Lower Clock Limit.
If you purchased ATS9360: Standard External Clock
Upgrade, Lower Clock Limit is 300 MHz.
If you purchased ATS9360: Screened External Clock
Upgrade, Lower Clock Limit is 75 MHz.
It is highly recommended that the Fast External Clock signal
have a duty cycle of 50% +/- 5%. However, duty cycle
specification can be substantially relaxed at lower
frequencies.
If the External Clock supplied is lower than the Lower Clock
Limit, measurement quality may be compromised.
Measurement errors may include gain errors, signal
discontinuities and general signal distortion.
External Clock must be a at least ±200mV sine wave or
square wave signal. Maximum amplitude for external clock is
±1V.
The receiver circuit for Fast External Clock is a high speed
ECL receiver that translates the input signal into a PECL
(Positive ECL) clock signal that features very fast rise times.
Since Fast External Clock is always ac-coupled and self-
biased, there is no need for the user to set the external clock
level.
Dummy Clock Switchover is another useful feature for OCT
applications that use Fast External Clock. In these
applications, the user-supplied clock is not of constant
frequency and may even be out of specification at certain
times.
The unique Dummy Clock Switchover capability of ATS9360
allows the sampling clock to be switched to a nominal 250
MHz clock while the user-supplied clock is out of
specification. User can control the switchover time by
supplying an appropriate pulse to AUX I/O connector.
