[AKD4953A-B]
<KM104800>
2010/10
- 4 -
(1-4) All interface signals including master clock are fed externally.
PORT3 (DSP) is used. Nothing should be connected to PORT2 (DIR).
JP11
MCKO
JP12
LRCK
JP13
ADC
DIR
JP16
BICK
JP14
BICK2
JP15
LRCK2
(2) Master mode
(2-1) Evaluation of Loop-back using MCLK of AK4118A
(2-2) Master clock is fed externally
(2-1) Evaluation of Loop-back using MCLK of AK4118A
X’tal oscillator (X1) is used. Nothing should be connected to PORT2 (DIR) and PORT3 (DSP).
It is possible to evaluate the AK4953A on Internal Loopback mode. (ADCPF=PFDAC bits= “1”)
It is possible to evaluate at various sampling frequencies using built-in AK4953A’s PLL.
JP11
MCKO
JP12
LRCK
JP13
ADC
DIR
JP16
BICK
JP14
BICK2
JP15
LRCK2
(2-2) Master clock is fed externally
PORT3 (DSP) is used and MCLK is fed from PORT3. Nothing should be connected to PORT2 (DIR).
It is possible to evaluate the AK4953A on Internal Loopback mode. (ADCPF=PFDAC bits= “1”)
It is possible to evaluate at various sampling frequencies using built-in AK4953A’s PLL.
JP11
MCKO
JP12
LRCK
JP13
ADC
DIR
JP16
BICK
JP14
BICK2
JP15
LRCK2
Summary of Contents for AKD4953A-B
Page 34: ...AKD4953A B KM104800 2010 10 34 fs 44 1kHz Figure 36 Crosstalk Plot Input level 1dBFS...
Page 39: ...AKD4953A B KM104800 2010 10 39 fs 96kHz Figure 45 Crosstalk Plot Input level 1dBFS...
Page 44: ...AKD4953A B KM104800 2010 10 44 fs 96kHz Figure 54 Crosstalk Plot Input level 1dBFS...
Page 49: ...AKD4953A B KM104800 2010 10 49 fs 96kHz Figure 63 Crosstalk Plot Input level 1dBFS...