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[AKD4753-A]

2) External Master Mode

(a)

Evaluation of D/A using DIR of AK4118A.

In case of AK4753 evaluation using AK4118A, it is necessary to correspond to audio interface format for

AK4753 and AK4118A.Please use AK4118A in the slave mode.

PORT1(RX) is used. Nothing should be connected to PORT3(DSP) and J7(MCKI).

EXT

DIR

JP4

AK4753-BICK

JP7

AK4753-MCLK

JP5

AK4753-SDATA

JP6

AK4753-LRCK

JP3

EXT

DIR

EXT

DIR

Figure 4. Setting of D/A using DIR of AK4118A

3) PLL Slave Mode

(a)

Evaluation of D/A using DIR of AK4118A.

In case of AK4753 evaluation using AK4118A, it is necessary to correspond to audio interface format for

AK4753 and AK4118A.Please use AK4118A in the master mode.

PORT1(RX) is used. Nothing should be connected to PORT3(DSP) and J7(MCKI).

EXT

DIR

JP4

AK4753-BICK

JP7

AK4753-MCLK

JP5

AK4753-SDATA

JP6

AK4753-LRCK

EXT

JP3

EXT

DIR

EXT

DIR

Figure 5. Setting of D/A using DIR of AK4118A

(b) All interface signals including master clock are fed externally.

PORT3(DSP) is used. Nothing should be connected to PORT1(RX) and J7(MCKI).

EXT

DIR

JP4

AK4753-BICK

JP7

AK4753-MCLK

JP5

AK4753-SDATA

JP6

AK4753-LRCK

EXT

JP3

EXT

DIR

EXT

DIR

JP17

MODE_SEL

SLAVE

MASTER

JP18

MCLK_SEL

MCLK

MUTEN

Figure 6. Setting of all interface signals including master clock are fed externally

KM103902

2011/01

- 4 -

Summary of Contents for AKD4753-A

Page 1: ...connectors for analog audio input output Optical connector for digital audio input On board digital audio interface AK4118A Potentiometers for Volume and Bass gain control USB connector for serial co...

Page 2: ...case JP15 is set to Open Should be always connected AGND Black Analog Ground GND Should be always connected DGND Black Digital Ground GND Table 1 Set up the power supply lines Each supply line should...

Page 3: ...K JP7 AK4753 MCLK JP5 AK4753 SDATA JP6 AK4753 LRCK MCKI DIR EXT JP3 XTL EXT GND EXT DIR EXT DIR Figure 2 Setting of D A using DIR of AK4118A b All interface signals including master clock are fed exte...

Page 4: ...118A it is necessary to correspond to audio interface format for AK4753 and AK4118A Please use AK4118A in the master mode PORT1 RX is used Nothing should be connected to PORT3 DSP and J7 MCKI EXT DIR...

Page 5: ...using J7 MCKI JP7 AK4753 MCLK MCKI DIR EXT JP3 XTL EXT GND JP7 AK4753 MCLK MCKI DIR EXT JP3 XTL EXT GND Figure 7 Setup the MCKI a 2 Other Setting BICK LRCK and SDATA PORT3 DSP is used Nothing should...

Page 6: ...e EXTEE switch See Table to L JP10 PC SDA JP8 PC SCL JP9 WP L Figure 9 Setting of EEP ROM operation1 2 When you load the setting from EEPROM to AK4753 Please change the EXTEE switch See Table 5 from t...

Page 7: ...tting of EEPROM SHORT Write protect is Disable OPEN Write protect is Enable Default JP10 PC SDA The selection of SDA signal SHORT When you write the setting in EEPROM OPEN When you load the setting fr...

Page 8: ...lt H L 512fs H H Not to use Table 3 Setting for AK4118A Master Clock Setting DIF2 DIF1 DIF0 SDTO LRCK BICK L L 24bit Left justified H L O 64fs O L H 24bit I2 S L H O 64fs O Fixed Default H L 24bit Lef...

Page 9: ...ringing L upon power up Indication for LED LED1 STO Monitor STO pin of the AK4753 LED turns on when Read error of EEPROM has occurred to AK4753 LED2 EFR Monitor INT0 pin of the AK4118A LED turns on wh...

Page 10: ...a AINL AINR C4 1u C2 1u J1 AINR AINR 1 2 3 4 5 J3 AINL 1 2 3 4 5 R3 open R1 open AINL Figure 12 Circuit diagram of AINL and AINR b SAIN1 SAIN2 SAIN1 AVDD R5 10k SAIN2 R7 10k C9 OPEN C12 OPEN Figure 13...

Page 11: ...ST2 LOUT R4 open C1 10u C5 10u C7 10u C10 10u R8 open C11 OPEN TEST4 ROUT J6 LOUT2 ROUT R6 open C8 OPEN TEST3 ROUT SW LOUT1 C3 OPEN TEST1 LOUT R2 open C6 OPEN ROUT1 TEST2 LOUT R4 open C1 10u C5 10u C7...

Page 12: ...PC When it can not be recognized correctly please Connect Evaluation board to PC with USB cable 3 Proceed evaluation by following the process below Operation Screen 1 Start up the control program foll...

Page 13: ...et by a hardware reset use this button to initialize the registers 3 All Write Executing write commands for all registers displayed 4 All Read Executing read commands for all registers displayed 5 Sav...

Page 14: ...A Tab Functions 1 Function Function control This tab is for function control Each operation is executed by the function buttons on the left side of the screen Figure 18 Window of Function KM103902 20...

Page 15: ...th Setting Refer to the datasheet for register settings of the AK4753 Figure 19 Window of Mode Setting 1 2 PLL Setting System Clock and Audio I F Setting When PLL Setting button is clicked the window...

Page 16: ...lide bars A register writing is made on every slide bar move After the volume slide is moved it is reflected on to the register map and data writing dialog box 1 3 2 Volume Control by Slide bar Slide...

Page 17: ...uch as HPF LPF and EQ filters a register writing and a frequency response checking of HPF LPF and EQ filters can be made When Digital Filter Setting button is clicked the window as shown in opens Refe...

Page 18: ...5x10 3 fon fs 0 4969 EQ1 5 Band Width Note 1 fbn fs 0 25 EQ1 5 Band Width EQ1 5 Gain Note 2 1 Gain 3 EQ1 5 Gain Table 6 Parameter Setting Note 1 A gain difference is a bandwidth of 3dB from center fre...

Page 19: ...f register setting is not carried out Figure 25 A register setting calculation result Followings are the cases when a register set value is updated 1 When Register Setting button was pushed 2 When F R...

Page 20: ...haracteristic is updated when push a UpDate button Figure 26 A frequency characteristic indication result Followings are the cases when a register set value is updated 1 When Register Setting button w...

Page 21: ...the operation of Center Frequency and Gain right clicking in the operation of the left click It moves by the left click After it moves a set value is reflected Figure 27 Filter Setting Left clicking...

Page 22: ...imiter Setting When Limiter Setting button is clicked the window as shown in opens This window is for Limiter Setting Refer to the datasheet for register settings of the AK4753 Figure 29 Window of Lim...

Page 23: ...indicates H or 1 and the bit name is in red when read only it is in deep red Button Up indicates L or 0 and the bit name is in blue when read only it is in gray Grayout registers are Read Only registe...

Page 24: ...the registers or click Cancel to cancel this setting Figure 31 Window of Register Set 2 2 Read Data Read Click Read button located on the right of the each corresponded address to execute register re...

Page 25: ...AKD4753 A 3 Tool Testing Tools This tab screen is for evaluation testing tool Click buttons for each testing tool Figure 32 Window of Tool KM103902 2011 01 25...

Page 26: ...alog Click Repeat Test button to open repeat test setting dialog box Figure 33 Window of Repeat Test 3 2 Loop Setting Loop Setting Dialog Click Loop Setting button to open loop setting dialog box Figu...

Page 27: ...s Writings are executed in descending order Help Help window is popped up Save Saving the register setting file assignment The file name is mar Open right Opening a saved register setting file assignm...

Page 28: ...adecimal numbers for data writing Data Box Input data in hexadecimal numbers Mask Box Input mask data in hexadecimal numbers This is AND processed input data Write Writing to the address specified by...

Page 29: ...1 Sequence Setting Set register sequence by following process bellow 1 Select a command Use Select pull down box to choose commands Corresponding boxes will be valid Select Pull down menu No_use Not u...

Page 30: ...ne 3 2 Control Buttons The function of Control Button is shown bellow Start Executing the sequence Help Opening a help window Save Saving sequence settings as a file The file name is aks Open Opening...

Page 31: ...in descending order Help Pop up the help window Save Saving sequence setting file assignment The file name is mas Open right Opening a saved sequence setting file assignment mas Close Closing the dia...

Page 32: ...rite button Register setting wrings to EEPROM The following messages are displayed according to the result of processing Writing failure Figure 40 Window of Writing failure Writing success Figure 41 W...

Page 33: ...ement Result 1 DAC a Single ended LOUT1 ROUT1 LOUT2 ROUT2 R Open L Result Result Parameter Unit Lch1 Rch1 Lch2 Rch2 S N D 88 7 88 1 88 3 88 1 dB 0dBFS Input D Range 99 2 98 7 99 2 98 3 dB 60dB Input A...

Page 34: ...4 86 3 86 5 86 3 dB 1dBFS Input D Range 95 1 95 0 95 1 95 0 dB 60dB Input A weighted S N 95 1 95 0 95 1 95 0 dB No Signal A weighted Open b Differential LOUT ROUT RL Result Parameter Unit Lch Rch S N...

Page 35: ...40 0 130 120 110 100 90 80 70 60 50 40 30 20 10 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 42 FFT 0dBFS Input AK4753 FFT LOUT1 ROUT1 fs 44 1kHz fin 1kHz 60dBFS Input External Slave Mode 140...

Page 36: ...70 60 50 40 30 20 10 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 44 FFT No Signal AK4753 THD N vs Input Level LOUT1 ROUT1 fs 44 1kHz fin 1kHz External Slave Mode 120 50 115 110 105 100 95 90...

Page 37: ...5 90 85 80 75 70 65 60 55 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 46 THD N vs Input Frequency AK4753 Linearity LOUT1 ROUT1 fs 44 1kHz fin 1kHz EXT Slave Mode 140 0 130 120 110 100 90 80 7...

Page 38: ...2 0 0 2 0 4 0 6 0 8 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 48 Frequency Response AK4753 Crosstalk LOUT1 ROUT1 fs 44 1kHz 0dBFS Input External Slave Mode 140 0 130 120 110 100 90 80 70 6...

Page 39: ...0 0 130 120 110 100 90 80 70 60 50 40 30 20 10 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 50 FFT 0dBFS Input AK4753 FFT LOUT ROUT fs 44 1kHz fin 1kHz 60dBFS Input External Slave Mode 140 0 1...

Page 40: ...70 60 50 40 30 20 10 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 52 FFT No Signal AK4753 THD N vs Input Level LOUT ROUT fs 44 1kHz fin 1kHz External Slave Mode 120 50 115 110 105 100 95 90 8...

Page 41: ...5 90 85 80 75 70 65 60 55 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 54 THD N vs Input Frequency AK4753 Linearity LOUT ROUT fs 44 1kHz fin 1kHz EXT Slave Mode 140 0 130 120 110 100 90 80 70...

Page 42: ...0 4 0 2 0 0 2 0 4 0 6 0 8 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 56 Frequency Response AK4753 Crosstalk LOUT ROUT fs 44 1kHz 0dBFS Input External Slave Mode 140 0 130 120 110 100 90 80 7...

Page 43: ...140 0 130 120 110 100 90 80 70 60 50 40 30 20 10 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 58 FFT 1dBFS Input AK4753 FFT LOUT1 ROUT1 fs 44 1kHz fin 1kHz 60dBFS Input 140 0 130 120 110 100...

Page 44: ...0 70 60 50 40 30 20 10 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 60 FFT No Signal AK4753 THD N vs Input Level LOUT1 ROUT1 fs 44 1kHz fin 1kHz 120 50 115 110 105 100 95 90 85 80 75 70 65 60...

Page 45: ...90 85 80 75 70 65 60 55 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 62 THD N vs Input Frequency AK4753 Linearity LOUT1 ROUT1 fs 44 1kHz fin 1kHz 140 0 130 120 110 100 90 80 70 60 50 40 30 20...

Page 46: ...1 4 1 2 1 0 8 0 6 0 4 0 2 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 64 Frequency Response AK4753 Crosstalk LOUT1 ROUT1 fs 44 1kHz 1dBFS Input 140 0 130 120 110 100 90 80 70 60 50 40 30 20...

Page 47: ...140 0 130 120 110 100 90 80 70 60 50 40 30 20 10 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 66 FFT 1dBFS Input AK4753 FFT LOUT ROUT fs 44 1kHz fin 1kHz 60dBFS Input 140 0 130 120 110 100 90...

Page 48: ...0 70 60 50 40 30 20 10 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 68 FFT No Signal AK4753 THD N vs Input Level LOUT ROUT fs 44 1kHz fin 1kHz 120 50 115 110 105 100 95 90 85 80 75 70 65 60 55...

Page 49: ...90 85 80 75 70 65 60 55 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 70 THD N vs Input Frequency AK4753 Linearity LOUT ROUT fs 44 1kHz fin 1kHz 140 0 130 120 110 100 90 80 70 60 50 40 30 20 10...

Page 50: ...6 1 4 1 2 1 0 8 0 6 0 4 0 2 d B r A 20 20k 50 100 200 500 1k 2k 5k 10k Hz Figure 72 Frequency Response AK4753 Crosstalk LOUT ROUT fs 44 1kHz 1dBFS Input 140 0 130 120 110 100 90 80 70 60 50 40 30 20 1...

Page 51: ...ritical componentsNote1 in any safety life support or other hazard related device or systemNote2 and AKM assumes no responsibility for such use except for the use approved with the express written con...

Page 52: ...1 5 Wednesday September 29 2010 J3 AINL J3 AINL 1 2 3 4 5 C4 1u C4 1u C7 10u C7 10u J4 ROUT1 J4 ROUT1 1 2 3 4 5 TEST2 LOUT TEST2 LOUT C11 OPEN C11 OPEN C1 10u C1 10u TEST3 ROUT TEST3 ROUT C8 OPEN C8...

Page 53: ...VDD TEST30 DVDD TEST17 SCL TEST17 SCL R17 0 R17 0 TEST21 STO TEST21 STO TEST37 VSS2 TEST37 VSS2 JP1 SAIN1 JP1 SAIN1 TEST22 ROUT1 TEST22 ROUT1 C25 0 1u C25 0 1u JP2 SAIN2 JP2 SAIN2 TEST26 LOUT2 TEST26...

Page 54: ...1A 1 3A 5 5A 11 5Y 10 3Y 6 1Y 2 2Y 4 4Y 8 6Y 12 6A 13 4A 9 2A 3 VCC 14 U4 AK4118A U4 AK4118A IPS0 RX4 1 NC 2 DIF0 RX5 3 TEST2 4 DIF1 RX6 5 VSS1 6 DIF2 RX7 7 IPS1 IIC 8 P SN 9 XTL0 10 XTL1 11 TVDD 13 N...

Page 55: ...F4550 TQFP 44 PIN U7 PIC18F4550 RC7 RX DT SDO 1 RD4 SPP4 2 RD5 SPP5 P1B 3 RD6 SPP6 P1C 4 RD7 SPP7 P1D 5 VSS0 6 VDD0 7 RB0 AN12 INT0 FLT0 SDI SDA 8 RB1 AN10 INT1 SCK SCL 9 RB2 AN8 INT2 VMO 10 RB3 AN9 C...

Page 56: ...C61 open JP13 AVDD JP13 AVDD J12 TJ 563 BLACK J12 TJ 563 BLACK 1 TK73633AME T2 TK73633AME T2 NC 1 Vout 2 PCL 3 GND 4 NC 8 Vin 7 NC 5 Vcont 6 C57 0 1u C57 0 1u C60 open C60 open R55 open R55 open C59...

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