ASAHI KASEI
[AKD4569]
<KM074000>
2004/02
- 3 -
n
Evaluation mode
Applicable evaluation modes
(1) Loopback mode
(2) Evaluation of A/D part
(3) Evaluation of D/A part (Default)
(4) All interface signals including master clock are fed externally.
Analog Output
(1),(2),(4)
(1),(3),(4)
PC
Printer Port
(2)
(3)
DSP
(4)
Digital Output
Digital Input
Analog Input
Power Supply
Unit
3V
J1
AINL
J2
AINR
J3
L/R/MIN
TOTX141
PORT4
TORX141
PORT2
DSP
PORT3
0V
µP I/F
PORT1
Analog Input
(3),(4)
VD
DGND AGND
DVDD HVDD
REG
AVDD
J4
MOUT
J5
HPL
J6
HP
J7
HPR
Figure 3. Connection diagram for each evaluation mode
<Setup of jumper pins, signal I/O connector and DIR for each evaluation mode>
Mode (1)
Mode (2)
Mode (3)
Mode (4)
JP6 (MCLK)
short
short
short
open
JP7 (SDTI)
ADC side
Don’t care
DIR side
open
JP8 (BICK)
short
short
short
open
JP9 (LRCK)
short
short
short
open
Signal input
J1(AINL), J2(AINR)
J1(AINL), J2(AINR)
PORT2(TORX141),
J3(LIN/RIN/MIN)
PORT3(DSP)
Signal output
J4(MOUT), J5(HPL),
J7(HPR), J6(HP)
PORT4(TOTX141)
J4(MOUT), J5(HPL),
J7(HPR), J6(HP)
J4(MOUT), J5(HPL),
J7(HPR), J6(HP)
AK4116(DIR)
Clock mode
(CM1-0 bit)
X’tal mode
(CM1-0 = “01”)
X’tal mode
(CM1-0 = “01”)
PLL mode
(CM1-0 = “00”)
X’tal mode
(CM1-0 = “01”)
Table 2. Setup of jumper pins etc. for each evaluation mode
