AKM AKD4552-A, Manual, Page: 6 / 33

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 6 -
3-3) Double speed (MCLK=256fs)
Master clock frequency example of X1 : X1 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2
MCKO
M2 M1
JP7
SPEED
JP9
MCLK
X2 X1 X4 X1
X4
X2
X1
X4 X1
JP10
BCFS
JP12
LRFS
JP11
CLK
DIR
EXT
XTL
SW2
MODE
1 2 3 4 5
DE
M0
DE
M1
OCK
S
0
OCK
S
1
CM
0
H
L
L
L
H
(4) Evaluation of D/A using A/D converted data
It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various
AKM’s A/D evaluation boards with PORT3 (ROM). Nothing should be connected to PORT1 (DIR). In case of
using external clock through a BNC connector (J5), select EXT on JP11 (CLK) and short JP8 (XTE) and open
JP13 (EXT). This mode corresponds to normal speed only.
JP3
LRCK
DIR ADC
JP4
BCLK
JP8
XTE
JP13
DIR ADC
JP6
SDTI
DIR ADC
EXT
•
Clock example
4-1) Normal speed of DAC (MCLK=256fs)
Master clock frequency example of X2 : X2 = 8.192MHz, 11.2896MHz, 12.288MHz
JP2
MCKO
M2 M1
JP7
SPEED
JP9
MCLK
X2 X1 X4 X1
X4
X2
X1
X4 X1
JP10
BCFS
JP12
LRFS
JP11
CLK
DIR
EXT
XTL
SW2
MODE
1 2 3 4 5
DE
M0
DE
M1
OCK
S
0
OCK
S
1
CM
0
H
L
L
L L
4-2) Normal speed of DAC (MCLK=512fs)
Master clock frequency example of X2 : X2 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2
MCKO
M2 M1
JP7
SPEED
JP9
MCLK
X2 X1 X4 X1
X4
X2
X1
X4 X1
JP10
BCFS
JP12
LRFS
JP11
CLK
DIR
EXT
XTL
SW2
MODE
1 2 3 4 5
DE
M0
DE
M1
OCK
S
0
OCK
S
1
CM
0
H
L L L L