AKM AKD4552-A, Manual, Page: 5 / 33

ASAHI KASEI [AKD4552-A]
<KM080600> 2005/10
- 5 -
2-4) 1/2 decimation of DAC (MCLK=128fs)
Input fs example for PORT1 : fs = 64kHz, 88.2kHz, 96kHz
JP2
MCKO
M2 M1
JP7
SPEED
JP9
MCLK
X2 X1 X4 X1
X4
X2
X1
X4 X1
JP10
BCFS
JP12
LRFS
JP11
CLK
DIR
EXT
XTL
SW2
MODE
1 2 3 4 5
DE
M0
DE
M1
OCK
S
0
OCK
S
1
CM
0
H
H
L L L
(3) Evaluation of loopback mode (default)
Using U4 (AK4112B) and X1 (X’tal). Nothing should be connected to PORT1 (DIR), PORT3 (ROM). Set up
“H” (AK4112B : X’tal mode) for SW2-5 (CM0).
JP3
LRCK
DIR ADC
JP4
BCLK
JP8
XTE
JP13
DIR ADC
JP6
SDTI
DIR ADC
EXT
•
Clock example
3-1) Normal speed (MCLK=256fs)
Master clock frequency example of X1 : X1 = 8.192MHz, 11.2896MHz, 12.288MHz
JP2
MCKO
M2 M1
JP7
SPEED
JP9
MCLK
X2 X1 X4 X1
X4
X2
X1
X4 X1
JP10
BCFS
JP12
LRFS
JP11
CLK
DIR
EXT
XTL
SW2
MODE
1 2 3 4 5
DE
M0
DE
M1
OCK
S
0
OCK
S
1
CM
0
H
L L L
H
3-2) Normal speed (MCLK=512fs)
Master clock frequency example of X1 : X1 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2
MCKO
M2 M1
JP7
SPEED
JP9
MCLK
X2 X1 X4 X1
X4
X2
X1
X4 X1
JP10
BCFS
JP12
LRFS
JP11
CLK
DIR
EXT
XTL
SW2
MODE
1
2 3 4 5
DE
M0
DE
M1
OCK
S
0
OCK
S
1
CM
0
H
L
L
H H