Akai PDP5006H, Service Manual

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Samsung SDI Co. Ltd. A/S Manual Plasma Display Module
To be Updated
3-2-2 Block Diagram for Logic circuit
1366×768 Pixels
1366×3×768 Cells
YP
uls
e
G
ene
ra
to
r
Ro
w
Dr
ive
r
Vsync
Enable
Hsync
DCLK
DRA
M
Dr
ive
r
Ti
min
g
C
on
tro
lle
r
Driver
Timing
Scan
Timing
Vs Va Vcc Vdd
DATA_R
8(9)Bits
Column Driver
Reference
- Vcc : Voltage for Logic Control
-Vdd : Voltage for FET driver
-Va : Voltage for address pulse
-Vsc_l: Voltage for sustain low
-Vscan: Voltage for scan high
-Vb
: Voltage for X bias
-Vset : Voltage for Y ramp pulse
DATA_G
8(9)Bits
DATA_B
8(9)Bits
In
put
D
ata
P
ro
ces
so
r
D
ata
C
on
tro
lle
r
XP
uls
e
G
ene
ra
to
r
Vset
Vscan
Vb
LVDS
Interface
Column Driver
Vsc_l
Display
Data
LOGIC CONTROL
DRIVER CIRCUIT & PANEL
3-3 Main function of Each Assembly
■
X-main board : The X-main board generate a drive signal by switching the FET in synchronization with logic
main board timing and supplies the X electrode of the panel with the drive signal through the
connector.
1) Maintain voltage waveforms (including ERC)
2) Generate X rising ramp signal
3) Maintain Ve bias between Scan intervals
■
.Y-main board : The Y-main board generate a drive signal by switching the FET in synchronization with the logic
Main Board timing and sequentially supplies the Y electrode of the panel with the drive signal
through the scan driver IC on the Y-buffer board. This board connected to the panel’s
Y terminal has the following main functions.
1) Maintain voltage waveforms (including ERC)
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