5.4 BLOCK DIAGRAM OF INTERFACE
CNF1
Rx3+
Rx3-
51
Ω
51
Ω
51
Ω
51
Ω
51
Ω
51
Ω
51
Ω
51
Ω
51
Ω
51
Ω
100pF
100pF
100pF
100pF
100pF
CLK-
CLK+
Rx2-
Rx2+
Rx1-
Rx1+
Rx0-
Rx0+
LVDS Receiver
THC63LVDF84A
LVDS Transmitter
THC63LVDM83A
(LVDF83A)
DCLK
Timing
Controller
DE
B0-B7
G0-G7
R0-R7
RxOUT
PLL
PLL
TxIN
Host
Graphics
Controller
DE
B0-B7
G0-G7
R0-R7
R0~R7 : Pixel R Data ,
G0~G7 : Pixel G Data ,
B0~B7 : Pixel B Data ,
DE : Data enable signal
Note (1) The system must have the transmitter to drive the module.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.
Version 1.0
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