34
33
IC BLOCK DIAGRAM-1
SCHEMATIC DIAGRAM-5 (MAIN 3/3 SECTION)
IC, LA1844L-A
IC, LC72131D
IC, BU1920FS
GND
GND
GND
MAIN C. B 3/3(TUNER SECTION)
L801
DC BALANCE/MONO
DISTORTION ADJ.
L802
AM IF ADJ.
L941,TC942
LW TRACKING ADJ.
L942
LW VT ADJ.
SIGNAL
: FM/PB
: AM
4C
1C
2C
3C
5C
6C
TU-ON
VCC
12
TUNER VM
TUNER-R
TUNER-L
STBY
7C
8C
9C
10C
11C
12C
13C
14C
15C
16C
17C
11.1
11.7
ON:8.7
OFF:0
5
SW
5
7.8
BUFFR
TU-ON
R986
2.2k 1/8W
1/8W
5.5
1/8W
TUNER
SW
TUNER VM
ON:8
OFF:0
12
TUNER-L
TUNER-R
TP4
1/8W
TP3
TP3,4
DC BALANCE
DECODER
FM DET-N
FM IF AMP
FM BAND SW
7.8
TP1
AM PACK2
L951(1/3)
MW TRACKING
ADJ.
FM
75
Ω
(COAXIAL)
MW/LW
LOOP
L941
ANT-LW
252K
TC942
30p
1
2
3
6
5
4
LW BAND
SW
D
G
L951(2/3)
AM PACK2
L951(3/3)
AM PACK2
L942
OSC LW
856k
Q953
2SK360 E
MW RF AMP
ON:8
OFF:0
ON:8,OFF:0
MW BAND SW
Q952
CSD1306 E
LW BAND SW
TO MAIN C.B 1/3(FUNCTION/POWER SUPPLY SECTION)1C-17C
+
1
2
16
5
14
8
7
6
15
9
11
12
10
13
3
4
100k
100k
100k
8TH SWITCHED
CAPACITOR FILTER
PLL
57kHz
RDS/ARI
PLL
1187.5HZ
REFERENCE
CLOCK
BI-PHASE
DECODER
TEST CIRCUIT
DIFFERENTIAL
DECODER
FO
CMP
ARI
RCLK
QUAR
RDATA
T57
T2
T1
XO
XI
VSS
VDD
Vref
MUX
RESET