-102-
IC BLOCK DIAGRAM -1/2
5
RAS
11
21
19
~
~
CAS
A0
A10
WE
DQ1~DQ4
12
V
CC
Generator
Internal
Address Counter
Row Address
Buffer
Memory
Cell
I/O
Selection
Write Clock
Generator
Data Input
Buffer
Data Output
Buffer
Row Address
Buffer
On ChipVBB
Generator
Row Decoder
Column Decoder
Sense Amp.
Word Driver
Refresh
Control Clock
4
OE
20
3
22
23
2
1
Timimg
Generator
Timimg
7
14
MODE
SW
BPF
BIAS
ADIP AGC
DIFF
RESISTOR & SW
EFM AGC
RF1
RF2
RF3
RF4
REFI
REFO
AOUT
ASW
AIN
BIN
BSW
BOUT
2-1
ADAGI
ADAGC
ADIPNF
ADIPO
GND2
WBO
VCC2
OPICPW
DISC
SGAIN
DTEMP
1234
1+2
PIN
3+4
PITG
NIN
GND1
BIAS
VCC1
EFMAGC
DCNF
EFMO
EOUT
ESW
EIN
FIN
FSW
FOUT
EOUT
BOUT
AOUT
TCGO
TCGI
RFADD
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
IC, IX2960AF
IC, IR3R58M