-57-
Pin No.
Pin Name
I/O
Description
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
77
78
79
80
81
82
VDDS
HDB6
HDB9
HDB5
VSS
HDBA
HDB4
HDBB
HDB3
VDDS
VDD
HDBC
HDB2
VSS
HDBD
HDB1
HDBE
HDB0
HDBF
HDRQ
VDDS
VSS
XHWR
XHRD
REDY
VDD
XHAC
HCS0
HCS1
DASP
VSS
C2PO
XRCI
—
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
—
—
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
O
—
—
I
I
O
—
I
I
I
I
I
I
I/O
—
I
I
Standard 5.0 V digital power supply terminal.
Host data bus [6].
Not used.
Host data bus [5].
Digital ground terminal.
Not used.
Host data bus [4].
Not used.
Host data bus [3].
Standard 5.0 V digital power supply terminal.
Standard 3.3 V digital power supply terminal.
Not used.
Host data bus [2].
Digital ground terminal.
Not used.
Host data bus [1].
Not used.
Host data bus [0].
Not used.
Positive logic output circuit of DMA data request to host.
Digital power supply terminal of standard 5.0 V.
Digital ground terminal.
Negative logic input signal of data write strobe from host.
Negative logic input signal of data read strobe from host.
Not used.
Standard 3.3 V digital power supply terminal.
DMA acknowledge negative logic input signal from host.
Not used.
Digital ground terminal.
Address input signal for internal register selection [1].
Open drain signal. Connected to PDIAG terminal of ATAPI.
Digital power supply terminal of standard 5.0 V.
Address input signal for internal register selection [0].
Address input signal for internal register selection [2].
Chip selection negative logic input signal from host [0].
Chip selection negative logic input signal from host [1].
Not used.
Digital ground terminal.
C2 pointer input signal from CD DSP.
RAM Over Flow input signal of CD DSP.
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9
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8
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9
8
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9
9
2
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2
9
8
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