– 2
3
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Description
Pin No.
Pin Name
I/O
Synchronization signal detection output pin.
78
FSEQ
O
Outputs a high level when the synchronization signal detected from the EFM signal
and the internally generated synchronization signal agree. (Not used)
79
DEFECT
I/O
Defect pin. Which becomes an input pin after reset and can be controlled externally. This becomes
the defect monitor pin under control by command. (Not used)
80
EFMO
O
EFM signal output pin. (Not used)
Summary of Contents for NSX-SZ6
Page 11: ...SCHEMATIC DIAGRAM 1 MAIN 1 3 11 ...
Page 12: ...SCHEMATIC DIAGRAM 2 MAIN 2 3 TUNER SECTION 12 ...
Page 13: ...SCHEMATIC DIAGRAM 3 MAIN 3 3 CD SECTION 13 ...
Page 14: ...SCHEMATIC DIAGRAM 4 FRONT 14 ...
Page 17: ... 17 IC BLOCK DIAGRAM ...
Page 18: ... 18 FL HNA 10SS15T GRID ASSIGNMENT ANODE CONNECTION GRID ASSIGNMENT ANODE CONNECTION ...