Pin No.
Pin Name
I/O
Description
-62-
1
2, 3
4
5, 6
7
8, 9
10
11, 12
13
14
15
16
17
18
19
20
21 ~ 24
25
26
27 ~ 32
33
34
35
45, 46
47
48, 49
50
VCC
DQ0, DQ1
VSSQ
DQ2, DQ3
VCCQ
DQ4, DQ5
VSSQ
DQ6, DQ7
VCCQ
LDQM
___
WE
____
CAS
____
RAS
___
CS
BA/A11
A10
A0 ~ A3
VCC
VSS
A4 ~ A9
NC
CKE
CLK
DQ12, DQ13
VSSQ
DQ14, DQ15
VSS
–
I/O
–
I/O
–
I/O
–
I/O
–
I
I
I
I
I
I
I
I
–
–
I
–
I
I
I
I/O
–
I/O
–
Power supply. Power supply for internal circuit and input buffer.
Data input/output. Multiplexed data input/output pin.
Ground. Power supply for DQ.
Data input/output. Multiplexed data input/output pin.
Data output power. Power supply for DQ.
Data input/output. Multiplexed data input/output pin.
Ground. Power supply for DQ.
Data input/output. Multiplexed data input/output pin.
Data output power. Power supply for DQ.
Data input/output mask. DQM control output buffer in read mode and mask input data in write
mode.
___
Write enable. WE defines the operation. Refer function truth table for details, Active "L".
____
Column address strobe. CAS defines the operation. Refer function truth table for details, Active
"L".
____
Row address strobe. RAS defines the operation. Refer function truth table for details, Active "L".
Chip select. Command input enable or mask except CLK, CKE and DQM. Active "L".
____
____
Bank address. Select either one of banks during both RAS and CAS activity.
Address. Row address: RA0 - RA10, column address: CA0 - CA7. Auto-precharge flag: A10.
Address. Row address: RA0 - RA10, column address: CA0 - CA7. Auto-precharge flag: A10.
Power supply. Power supply for internal circuit and input buffer.
Ground. Power supply for internal circuit and input buffer.
Address. Row address: RA0 - RA10, column address: CA0 - CA7. Auto-precharge flag: A10.
Not connected.
Clock enable. Controls internal clock signal and when deactivated, the SDRAM will be one of
the states among power down, suspend or self refresh.
Clock. The system clock input. All other inputs are referenced to the SDRAM on the rising edge
of CLK.
Data input/output mask. DQM control output buffer in read mode and mask input data in write
mode.
Not connected.
Data output power. Power supply for DQ.
Data input/output. Multiplexed data input/output pin.
Ground. Power supply for DQ.
Data input/output. Multiplexed data input/output pin.
Data output power. Power supply for DQ.
Data input/output. Multiplexed data input/output pin.
Ground. Power supply for DQ.
Data input/output. Multiplexed data input/output pin.
Ground. Power supply for internal circuit and input buffer.
IC DESCRIPTION -9/9 (HY57V161610DTC8) -1/1
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