25
25
CA-V100
6-2. BLOCK DIAGRAM — VCD SECTION —
A
C
B
D
VC
VREF
LD
PD
F
E
LD
VREF
PD1
RFO
FE
TE
AGC
CONT
IC1004,1005
PD2
E
F
VREF
PD
7
8
10
PD
LD ON
3
5
2
15
13
11
4
1
2
TRACKING
COIL
DRIVE
FOCUS
COIL
DRIVE
SLED
MOTOR
DRIVE
SPINDLE
MOTOR
DRIVE
12
13
16
17
27
26
TRACKING
COIL
FOCUS
COIL
OPTICAL PICK-UP
BLOCK
(KSS-213R)
M
M
M1002
SLED
MOTOR
M1001
SPINDLE
MOTOR
A
LD
DRIVE
5
9
20
19
24
4
10
15
AGC
ASYMMETRY
CORRECT/
DIGITAL PLL
FEM DEM/
ERROR
CORRECT/
RAM
18
19
50
39
41
40
43
72
71
58
59
33
34
31
32
29
30
25
2
D/A
I/F
GAIN
CONTROL
66
67
65
14
CPU
I/F
Q1003
IC1001
CD SERVO/CD DSP
IC1002
RF AMP
76
77
15
79
80
4
6
5
7
8
26
22
13
10
SUB
CODE
PROCESS
SERVO
AUTO
SEQUENCE
DIGITAL
CLV
SERVO
I/F
SERVO
BLOCK
IC1003
COIL/MOTOR
DRIVER
6
1
12
110
31
30
120
118
122
114
121
113
106
100
115
102
101
105
14
104
55
57
56
125
60
3
59
4
58
2
61
1
12
11
10
9
16
18
17
20
24
22
4
14
13
8
4
18
11
CLK
SW1001
6Q
LIMIT/AGC
GAIN UP
5D
4D
2D
8D
3.3V
8
7
6
5
2
3
3
80
2
19
10
107
11
96
5
15
6Q
5Q
4Q
2Q
8Q
12
9
5
19
21 – 28
LD0-LD7
LA0-LA18
33 – 40
43 – 53
D0-D7
OE#
CE#
A0-A18
13 – 15
17 – 21
2-12,23
25-31
68
67
14
15
79-84
69-78
DBUS0
I
DBUS15
MA0-MA9
DQ0-DQ15
A0-A9
18 – 21
24 – 29
2-5,7-10
35-38,40-43
62
31
32
LPF
SERVO
I/F
J501
Q501,502
IC1010
IC1007
EPROM
IC1009
DRAM
LD5
LD4
LD3
LD1
LD7
IC1011
D-F/F
VDAC
TDMDR
TDMCLK
TDMFS
AUX24
SDTI
1
R-CH
LRCK
BICK
MCLK
CDTI
CCLK
CSN
PDN
L+
3
2
CD-L
IC305
IC1012
AUDIO DAC
IC1006
VCD
L–
R+
R–
AUX21
AUX22
AUX17
AUX20
AUX26
AUX15
AUX00
AUX02
XIN
XOUT
WE
RAS
CASH
CASL
AUX12
AUX07
AUX05
AUX27
AUX06
REST#
AUX03
AUX16
AUX04
AUX31
AUX25
TSD
TWS
TBCK
MCLK
LWR#
CSD#
LOEW
CS3#
DWE#
DRAS#
CAS#
I-CD DOOR
I-VIDEO
S801
CD OPEN
PAL
NTSC
S501
NTSC/PAL
I-CD DATA
XRST
MDP
SRDR
SFDR
FRDR
TFDR
FFDR
XTAI
XTAO
SE
TE
RFDC
FE
RFAC
TRDR
FOK
SCLK
SSTP
SENS
XLAT
CLOK
DATA
SCOR
EXCK
SBSO
SQCK
SQSO
WFCK
GFS
C2PO
LRCK
BCK
PCMD
I-CD ACK
O-CD DATA
O-CD STB
O-VCD RESET
VIDEO OUT
Q1002
LD
DRIVE
Q1001
X1002
27MHz
X1001
16.9344MHz
IC1013
BUFFER
IC801 (1/3)
SYSTEM CONTROL
MUTE
• Signal path
: CD
• R-ch is omitted due to same as L-ch.
(Page 27)
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