Aiwa AV-D67, Service Manual, Page: 31 / 35

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1 AVDD - Analog power supply for PLL (+5V).
2 PCO - PLL filter connection terminal.
3 AVSS - Analog ground.
4 M/S I Master / slave mode selection. (Not used)
5 DDIN I Digital audio interface data input.
6 TEST I Test terminal (To be open). (Not used)
7 /IC I Initial clear input.
8 VSS - Ground.
9 XO O 24.576MHz crystal oscillator connection output terminal.
10 XI I 24.576MHz crystal oscillator connection input terminal.
11 MCK O 12.288MHz clock output.
12 VDD -
+5V power supply.
13 SDO O Serial data output.
14 SDBCK I/O
Serial data bit clock input / output (64 fs).
15 SDWCK I/O Serial data word clock input / output (fs).
16 SDMCK O Serial data master clock output (256 fs or 128 fs).
17 VSS - Ground.
18 SYNC/U O Serial data synchronization timing output / User data output. (Not used)
19 FS128/C O
Serial data master clock 128 fs output / Channel status output. (Not used)
20 DBL/V O Double rate output / Validity flag output.
21 ERR/BS O Data error detection output / Block start output. (Not used)
22 /LOCK O PLL lock detection output.
23 INT O
Interrupt output.
24 VDD
-
+5V power supply.
25 /CS I Microcomputer interface chip select input.
26 SO O Microcomputer interface data output.
27 SI I Microcomputer interface data input.
28 SCK I Microcomputer interface bit clock input.
Pin No. Pin Name I/O Description
IC, YSD917