Revision B • 7/00
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5
4 Equipment Description
The DSP is based on Motorola’s 24-bit fixed
point DSP integrated circuits. 24-bit data words
provide 144 dB of dynamic range. The DSP oper-
ates at a nominal sample rate of 48 kHz with on-
board crystal synchronization. The internal reso-
lution of 56-bits provides 336 dB of computational
dynamic range.
Two DSP options are available from the factory:
44.1 kHz internal sampling and/or external AES-
11 reference.
The left hand DSP card (DSP 1) connects to
the first eight Input module positions (see 92-1007,
P12 for its connector pin-out) on both the AWD-
12 and the AWD-20. Each of the first eight Input
module positions connect their SDATA outputs,
along with their switch outputs and fader wiper
voltage, directly to the DSP board. When the Fader
Start Logic option is enabled on the Output mod-
ule, a control signal from the DSP (FADER_ON)
is used to turn on the module as the fader is moved
from its full off position.
On the AWD-20, the next eight channels (in-
puts 9 - 16) connect to DSP 2, identical to DSP 1
except for its EPROM.
The right-hand DSP (DSP 3) handles the re-
maining four Input module positions for each size
console and the two Telco positions (which may
alternately have Input modules installed). This
DSP also creates the main digital output
(MIX_SDATA) and the meter outputs (DISPLAY
SERIAL DATA 1 and 2). See schematic 92-1009,
P12 for pin out information for DSP 3.
Each DSP board is linked to the other(s) via a
6-conductor flex cable on the motherboard. Each
board generates its own DSP Go and Fader High
and Low reference signals. DSP 1 generates the
system clocks and system reset signals.
OUTPUT MODULE
Refer to the six Output Amplifier module sche-
matics (92-1006) in Chapter 6.
The right-hand DSP board outputs the
MIX_SDATA digital data stream to the Output
module FPGA (U9). The FPGA (see 92-1006, page
6 of 6) divides the individual data streams carried
within the multiplexed data to form the cue and
off-line buses (CUE/TEL_ STRMB), and the three
individual program buses (PGM1_STRMB,
PGM2_STRMB, PGM3_ STRMB) from this mul-
tiplexed input.
The various Program 1 outputs are on 92-1006,
page 1 of 6. The PGM1_STRMB (from the FPGA)
drives U22, an AES/EBU transmitter, and U25, a
DAC (Digital-to-Analog Converter).
The AES/EBU chip converts the serial data into
an AES-3 compatible signal that is transformer
(T1) coupled to the Pgm-1 digital output. There
are no level adjustments on the digital outputs.
The DAC’s left and right outputs are capaci-
tively-coupled to the two buffers in U1. Output
trim controls, RV2 and RV3, set the output level
of the right and left channels, respectively, for a
n4 dBu. Output amplifiers U6, U7, U8
and U10 create the balanced Main and Aux out-
puts. The Aux output is resistor-isolated from the
Main output. The Pgm-1 Monitor output is con-
nected (via the supplied patch cord) to the Pgm-1
monitor selector input on the Monitor module.
The Program 2 output is on page 2 of the sche-
matic. It is identical to the Program 1 output with-
out the additional Monitor output (the monitor-
ing connection is done via the motherboard to the
Monitor module).
The Program 3 output is on page 3 of the sche-
matic. It is identical to the Program 2 output, ex-
cept it does not have an Aux output.
The two Mono outputs (Main and Aux) are se-
lected from among the three program buses by
U36, a three-input analog switch. The left and right
channel inputs come from the DAC buffer outputs
on each program amplifier. U36 is controlled by
the three faceplate program select switches. The
