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Chapter 3. Hardware Settings
SB101-UR User Manual
17
Slimline Connector 0 (J48)
Pin Description
Pin Description
A1 Ground
B1 Ground
A2 PCH_SATA_RX_P0_C_DP
B2 PCH_SATA_TX_P0_C_DP
A3 PCH_SATA_RX_P0_C_DN
B3 PCH_SATA_TX_P0_C_DN
A4 Ground
B4 Ground
A5 PCH_SATA_RX_P1_C_DP
B5 PCH_SATA_TX_P1_C_DP
A6 PCH_SATA_RX_P1_C_DN
B6 PCH_SATA_TX_P1_C_DN
A7 Ground
B7 Ground
A8 SGPIO_SATA_DATA0
B8 SGPIO_SATA_CLOCK
A9 TP_SATA0_RSVD_A9
B9 SGPIO_SATA_LOAD
A10 Ground
B10 Ground
A11 TP_SATA0_RSVD_A11
B11 TP_SATA0_RSVD_B11
A12 TP_SATA0_RSVD_A12
B12 NC
A13 Ground
B13 Ground
A14 PCH_SATA_RX_P2_C_DP
B14 PCH_SATA_TX_P2_C_DP
A15 PCH_SATA_RX_P2_C_DN
B15 PCH_SATA_TX_P2_C_DN
A16 Ground
B16 Ground
A17 PCH_SATA_RX_P3_C_DP
B17 PCH_SATA_TX_P3_C_DP
A18 PCH_SATA_RX_P3_C_DN
B18 PCH_SATA_TX_P3_C_DN
A19 Ground
B19 Ground
CPU0
CPU1
5
26
45
16
17
18