19
Chapter 2
2.5.4 IRQ Level
The IRQ level is by default set by the system BIOS. IRQ 7 is reserved for
DI interrupt and counter interrupt.
2.5.5 Interrupt Control Register
The Interrupt Control Register controls the function and status of each
interrupt signal source. Table 2.13 shows the bit map of the Interrupt Con-
trol Register. The register is readable/writeable register. While being writ-
ten, it is used as a control register; and while being read, it is used as a sta-
tus register.
DI0EN & DI1EN: DI0 & DI1 Interrupt disable/enable control bit
DI0TE & DI1TE: DI0 & DI1 Interrupt triggering edge control bit
DI0F & DI1F: DI0 & DI1 interrupt flag bit
2.5.6 Interrupt Enable Control Function
The user can choose to enable or disable the interrupt function by writing
its corresponding value to the interrupt disable/enable control bit in the
interrupt control register, as shown in Table 2.14.
Table 2.2: Interrupt Control Register Bit Map
Base Address
7
6
5
4
3
2
1
0
202H
R/W
Interrupt Enable Control/Status Register
DI1EN DI0EN
203H
R/W
Interrupt Triggering Edge Control/Status Register
DI1TE
DI0TE
207H
R/W
Interrupt Flag/Clear Register
DI1F
DI0F
Table 2.3: Interrupt Disable/Enable Control
DI0EN & DI1EN
Interrupt Disable/Enable Control
0
Disable
1
Enable
Summary of Contents for UNO-3082
Page 10: ...UNO 3084 User Manual x...
Page 18: ...UNO 3084 User Manual 8...
Page 48: ...UNO 3084 User Manual 38...
Page 54: ...UNO 3084 User Manual 44 5 Plug in PCI bus card in a PCI slot of UNO 3084...
Page 59: ...APPENDIX A System Settings and Pin Assignments...
Page 76: ...UNO 3084 User Manual 66...
Page 77: ...APPENDIX B Programming the Watchdog Timer...
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