Advantech UBC-220, User Manual, Page: 49 / 62

41 UBC-220 User Manual
Chapter 3
S
oftware
Functionality
3.8.3 RS232 Initial Code
The RS232 initial code as below. It shows you how to initialize COM2 ports.
int open_port(void)
{
int fd;
fd=open("/dev/ttymxc1",O_RDWR|O_NOCTTY|O_NDELAY);
if(fd == -1){
perror("open error");
}
return(fd);
}
3.8.4 Display Output Setting
3.8.4.1 Single Display Settings
HDMI out, please set in u-boot as below:
setenv bootargs_base 'setenv bootargs console=ttymxc0,115200
enable_wait_mode=off
video=mxcfb1:off video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24
video_mode=display3 pcie_testmode=off'
LVDS (Single) out, please set in u-boot as below:
setenv bootargs_base 'setenv bootargs console=ttymxc0,115200
enable_wait_mode=off
video=mxcfb1:off video=mxcfb0:dev=ldb,800x480M@60,if=RGB24
video_mode=display3 pcie_testmode=off'
3.8.4.2 Dual Display Settings
When you want to display LVDS and HDMI output , please set parameter in U-boot
as following. This is the default settings in U-boot.
setenv bootargs_base 'setenv bootargs console=ttymxc0,115200
enable_wait_mode=off video_mode=display3 pcie_testmode=off'
For display interface clock, there are several options (Independently for each port)
listed below:
1. Derived from the IPU internal clock (Master Mode)
2. Provided by an external source (Slave Mode)
3. The transfer rate supported
When a single port is active, the pixel clock rate is up to 264 MHz
When both LVDS ports are active, you have to follow below condition:
1) Each pixel clock rate may be up to 220 MHz**
2) The sum of pixel clock rates is up to 240 MHz
Note! Specified pixel clocks frequencies are applicable for internal clocks, but
may be limited by IO buffers speed capability. Final numbers are sub-
jected to AC characterization.