Advantech SOM-5993, User Manual

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SOM-5993 User Manual 8
PCIe x8, [7:0]
Intel
®
Xeon
®
Processor D natively integrates 1 x PCI express x8 lanes and up to 4 x
devices at up to Gen3 speeds (8.0 GT/s).
SOM-5993 supports 1 PCIe x4 and 2 x2 in default, and is configurable to 4 x2, 1 x4
and 2 x2, 2 x2 and 1 x4 or 2 x4, 1 x8.
PCIe x8, [15:8]
Intel
®
Xeon
®
Processor D natively integrates 1 x PCIe x8 lanes and up to 4 x devices
at up to Gen3 speed (8.0 GT/s).
SOM-5993 supports 1 x PCIe x8 by default, and is configurable to 4 x2, 1 x4 and 2
x2, 2 x2 and 1 x4 or 2 x4.
1.3.7 LPC
This solution supports Low Pin Count (LPC) 1.1 specifications, without DMA or bus
mastering. This allows it to connect super I/O, embedded controllers, or TPM. LPC
clock is 25MHz.
1.3.8 Serial Bus
1.3.8.1 SMBus
Support SMBus 2.0 specifications with alert pins.
1.3.8.2 I2C Bus
Supports I2C bus 8-bit and 10-bit address modes, at both 100KHz and 400KHz.
Type 7
Row A,B Row C,D
P0 P1 P2 P3 P4 P5 P6 P7
Default
Config.
X4 X2 X2
Option 1 X2 X2 X2 X2
Option 2 X4 X2 X2
Option 3 X2 X2 X4
Option 4 X4 X4
Option 5 X8
Type 7
Row A,B
P8 P9 P10 P11 P12 P13 P14 P15
Default
Config
X8
Option 1 X2 X2 X2 X2
Option 2 X4 X2 X2
Option 3 X2 X2 X4
Option 4 X4 X4
Option 5 X8