Advantech SOM-5992 Design Manual Download

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１２３

Figure 37

: AT Style Power Up Boot

Table 50

: Power Management Timings

Sym

Description

Min

Max

Power Button

16ms

The power-on time is defined as the time from when PS_ON# is pulled low
to when the VCC_12V, VCC_5V and VCC_3V output.

500ms

VCC_12V rise time from 10% to 95%

0.1ms

20ms

PWR_OK delay

100ms

PWR_OK rise time

10ms

See Note 1

Power-down warning

1ms

VCC_5V_SBY (To COMe)

(Optional)

PWR_BTN# (To COMe)

(Optional)

SUS_S3# (From COMe)

VCC_12V (To COMe)

10%

95%

VCC_5V, VCC3V

For Carrier Board use

(not needed by Module)

PWR_OK (To COMe)

Module Intermal Power Rails

SYS_RESET# (To COMe) (Optional)

CB_RESET# (From COMe)

Power Down

Summary of Contents for SOM-5992

Page 1: ...SOM 5992 COMe TYPE7 R1210 2018 09 25...

Page 2: ...n Loss Budget with Slot Card 2 3 3 2 PCI Express Insertion Loss Budget with Carrier Board PCIE Device 2 3 4 PCI Express Trace Length Guidelines 2 4 NC SI 2 4 1 NC SI Signal Definitions 2 4 2 NC SI Gen...

Page 3: ...0 2 8 1 USB3 0 Signal Definitions 2 8 1 1 USB Over Current Protection USB_x_y_OC 2 8 1 2 EMI ESD Protection 2 8 2 USB3 0 Routing Guidelines 2 8 3 USB3 0 Trace Length Guidelines 2 9 SATA 2 9 1 SATA Si...

Page 4: ...ce SOM 5992 is not support CAN Interface 2 15 1 CAN interface Signal Definitions 2 15 2 CAN interface Routing Guidelines 2 15 3 CAN interface Trace Length Guidelines 2 16 Miscellaneous Signals 2 16 1...

Page 5: ...12 NC SI Trace Length Guidelines Table 13 10GB LAN Signal Description Table 14 I2C Data Mapping to Carrier Board based PCA9539 I O expander Table 15 10 100 1000 Ethernet Insertion Loss Budget 100 MHz...

Page 6: ...able 41 CAN interface Signal Definitions Table 42 CAN interface Trace Length Guidelines Table 43 Miscellaneous Signal Definitions Table 44 Signal Definition SDIO Table 45 Power Management Signal Defin...

Page 7: ...0G Ethernet AC coupling backplane system Figure 13 10G Ethernet AC coupling direct cable Figure 14 10G Ethernet AC coupling PHY on Carrier Figure 15 10GBASE KR Trace Length Budget Figure 16 10 100 100...

Page 8: ...Figure 33 Topology for Serial interface Figure 34 Topology for CAN interface Figure 35 Topology for SDIO Figure 36 ATX Style Power Up Boot Controlled by Power Button Figure 37 AT Style Power Up Boot...

Page 9: ...Output 3 3V signal level O 5V Output 5V signal level OD Open drain output P Power input output S0 S1 S2 S3 S4 S5 System states describing the power and activity level S0 Full power all devices powere...

Page 10: ...al functions System information Watchdog timer I2C Bus Flat Panel brightness control User storage area GPIO EEPROM Electrically Erasable Programmable Read Only Memory eSPI Enhanced Serial Peripheral I...

Page 11: ...Express next generation high speed Serialized I O bus PEG PCI Express Graphics PHY Ethernet controller physical layer device Pin out Type A reference to one of seven COM Express definitions for the si...

Page 12: ...ation information SPI Serial Peripheral Interface Super I O An integrated circuit typically interfaced via the LPC bus that provides legacy PC I O functions including PS2 keyboard and mouse ports seri...

Page 13: ...esign Guide Rev 2 01 1 4 Revision History Revision Date PCB Rev Changes 0 10 2017 02 14 A101 1 1 00 2017 10 02 A101 2 1 Change NC SI interface connection from 10G to GbE0 add GbE0 SDP Pin connection t...

Page 14: ...t Type BGA 37 5 x37 5 P1272 0 7mm pitch Pins 1667 Processor Type Microserver Intel Xeon D 1500 Series SoC BDW DE MaxLast Level Cache per Cbo 1 5 MB Number of cores 8 or 16 based on SKU PCIE 7 1 xPCIEx...

Page 15: ...anes 6 15 0 10 10 PCI Express Lanes 16 31 0 16 16 10G LAN Ports 0 3 0 4 2 NC SI 0 1 1 1Gb LAN Port 0 1 1 1 Serial Ports 1 2 0 2 2 CAN interface on SER1 0 1 0 SATA Ports 0 2 2 USB 2 0 Ports 4 4 4 USB0...

Page 16: ...Feature Type 7 Min Max SOM 5992 Power Good 1 1 1 VCC_5V_SBY Contacts 4 4 4 Sleep Input 0 1 1 Lid Input 0 1 1 Carrier Board Fan Control 0 1 1 Power VCC_12V Contacts 24 24 24...

Page 17: ...2 COM Express Type 7 Interfaces 2 1 COM Express Type 7 Connector Layout Figure 2 COM Express Type7 Connector Layout NA...

Page 18: ...PI_ALERT0 LPC_DRQ0 A9 GBE0_MDI1 B9 LPC_DRQ1 ESPI_ALERT1 LPC_DRQ1 A10 GBE0_MDI1 B10 LPC_CLK ESPI_CK LPC_CLK A11 GND FIXED B11 GND FIXED A12 GBE0_MDI0 B12 PWRBTN A13 GBE0_MDI0 B13 SMB_CK A14 GBE0_CTREF...

Page 19: ...2_3_OC B44 USB_0_1_OC A45 USB0 B45 USB1 A46 USB0 B46 USB1 A47 VCC_RTC B47 ESPI_EN NC A48 RSVD B48 USB0_HOST_PRSNT NC A49 GBE0_SDP B49 SYS_RESET A50 LPC_SERIRQ ESPI_CS1 LPC_SERIRQ B50 CB_RESET A51 GND...

Page 20: ...A81 PCIE_TX11 B81 PCIE_RX11 A82 PCIE_TX11 B82 PCIE_RX11 A83 GND B83 GND A84 NCSI_TX_EN B84 VCC_5V_SBY A85 GPI3 B85 VCC_5V_SBY A86 RSVD B86 VCC_5V_SBY A87 RSVD B87 VCC_5V_SBY A88 PCIE_CLK_REF B88 BIOS...

Page 21: ...fference Pin Type 7 Description SOM 5992 Difference A103 LID B103 SLEEP A104 VCC_12V B104 VCC_12V A105 VCC_12V B105 VCC_12V A106 VCC_12V B106 VCC_12V A107 VCC_12V B107 VCC_12V A108 VCC_12V B108 VCC_12...

Page 22: ...PHY_MDIO_SDA3 NC C16 10G_PHY_MDC_SCL2 NC D16 10G_PHY_MDIO_SCL2 NC C17 10G_SDP2 NC D17 10G_SDP3 NC C18 GND D18 GND C19 PCIE_RX6 D19 PCIE_TX6 C20 PCIE_RX6 D20 PCIE_TX6 C21 GND FIXED D21 GND FIXED C22 PC...

Page 23: ...T1 C48 GND D48 GND C49 10G_KR_RX0 D49 10G_KR_TX0 C50 10G_KR_RX0 D50 10G_KR_TX0 C51 GND FIXED D51 GND FIXED C52 PCIE_RX16 D52 PCIE_TX16 C53 PCIE_RX16 D53 PCIE_TX16 C54 TYPE0 GND D54 RSVD C55 PCIE_RX17...

Page 24: ...SVD D83 RSVD C84 GND D84 GND C85 PCIE_RX26 D85 PCIE_TX26 C86 PCIE_RX26 D86 PCIE_TX26 C87 GND D87 GND C88 PCIE_RX27 D88 PCIE_TX27 C89 PCIE_RX27 D89 PCIE_TX27 C90 GND FIXED D90 GND FIXED C91 PCIE_RX28 D...

Page 25: ...r Rows C and D Pin Type 7 Description SOM 5992 Difference Pin Type 7 Description SOM 5992 Difference C107 VCC_12V D107 VCC_12V C108 VCC_12V D108 VCC_12V C109 VCC_12V D109 VCC_12V C110 GND FIXED D110 G...

Page 26: ...ct to PCIE0 x1 Conn pin A16 A17 PERp n0 N C if not used I PCIE 2 PCIE_TX0 PCIE_TX0 A68 A69 PCIe channel 0 Transmit Output differential pair Module has integrated AC Coupling Capacitor Carrier Board De...

Page 27: ...E 2 PCIE_RX3 PCIE_RX3 B58 B59 PCIe channel 3 Receive Input differential pair Carrier Board Device Connect AC Coupling cap 0 1uF near to PCIE3 x1 device PETp n0 Slot Connect to PCIE3 x1 Conn pin A16 A1...

Page 28: ...PCIE_TX5 A52 A53 PCIe channel 5 Transmit Output differential pair Module has integrated AC Coupling Capacitor Carrier Board Device Connect to PCIE5 x1 device PERp n0 Slot Connect to PCIE5 x1 Conn pin...

Page 29: ...71 B71 PCIe channel 8 Receive Input differential pair Carrier Board Device Connect AC Coupling cap 0 1 0 22uF near to PCIE device PETp nX N C if not used I PCIE 3 PCIE_TX8 PCIE_TX8 A71 A72 PCIe channe...

Page 30: ...le has integrated AC Coupling Capacitor Carrier Board Device Connect to PCIE device PERp nX N C if not used O PCIE 3 PCIE_RX12 PCIE_RX12 B39 B40 PCIe channel 12 Receive Input differential pair Carrier...

Page 31: ...le has integrated AC Coupling Capacitor Carrier Board Device Connect to PCIE device PERp nX N C if not used O PCIE 3 PCIE_RX16 PCIE_RX16 C52 C53 PCIe channel 16 Receive Input differential pair Carrier...

Page 32: ...le has integrated AC Coupling Capacitor Carrier Board Device Connect to PCIE device PERp nX N C if not used O PCIE 3 PCIE_RX20 PCIE_RX20 C65 C66 PCIe channel 20 Receive Input differential pair Carrier...

Page 33: ...le has integrated AC Coupling Capacitor Carrier Board Device Connect to PCIE device PERp nX N C if not used O PCIE 3 PCIE_RX24 PCIE_RX24 C78 C79 PCIe channel 24 Receive Input differential pair Carrier...

Page 34: ...le has integrated AC Coupling Capacitor Carrier Board Device Connect to PCIE device PERp nX N C if not used O PCIE 3 PCIE_RX28 PCIE_RX28 C91 C92 PCIe channel 28 Receive Input differential pair Carrier...

Page 35: ...p 0 1 0 22uF near to PCIE device PETp nX N C if not used I PCIE 3 PCIE_TX31 PCIE_TX31 D101 D102 PCIe channel 31 Transmit Output differential pair Module has integrated AC Coupling Capacitor Carrier Bo...

Page 36: ...5 X1 A53 PCIE_TX5 B53 PCIE_RX5 D19 PCIE_TX6 C19 PCIE_RX6 PCIE1X6 X1 D20 PCIE_TX6 C20 PCIE_RX6 D22 PCIE_TX7 C22 PCIE_RX7 PCIE1X7 Default I210 Option X1 D23 PCIE_TX7 C23 PCIE_RX7 A71 PCIE_TX8 B71 PCIE_R...

Page 37: ...16X6 D72 PCIE_TX22 C72 PCIE_RX22 D74 PCIE_TX23 C74 PCIE_RX23 PCIE16X7 D75 PCIE_TX23 C75 PCIE_RX23 D78 PCIE_TX24 C78 PCIE_RX24 PCIE16X8 X4 X8 D79 PCIE_TX24 C79 PCIE_RX24 D81 PCIE_TX25 C81 PCIE_RX25 PCI...

Page 38: ...d for separately The Carrier Board transmit and receive insertion loss budgets are the same in this case The Carrier Board insertion loss budget shall be 4 40 dB COM Express connector and slot card co...

Page 39: ...Module PCIe maximum trace length is restricted to 5 0 inches and the Carrier Board maximum trace to 4 45 inches Shorter lengths will yield additional margin and are encouraged where possible Results a...

Page 40: ...ier Board trace lengths and more Carrier Board design flexibility The Module and COM Express connector loss budgets remain the same Figure 4 PCI Express Insertion Loss Budget with Carrier Board PCIe D...

Page 41: ...s PCI Express Insertion Loss Budget 2 5 GHz with Carrier Board PCIE Device For device down PCIe Gen 2 operation the Module PCIe maximum trace length is restricted to 5 0 inches and the Carrier Board m...

Page 42: ...2 3 4 PCI Express Trace Length Guidelines Figure 5 Topology for PCI Express Slot Card Figure 6 Topology for PCI Express Device Down...

Page 43: ...referencing preferred Min 40 mil trace edge to major plane edge spacing GND stitching vias required next to signal vias if transitioning layers between GND layers Power referencing acceptable if stitc...

Page 44: ...r to use hardware based arbitration NCSI_ARB_IN and NCSI_ARB_OUT are to be left unconnected on the Carrier if there is no Carrier network controller Table 11 NC SI Signal Description Signal Pin Descri...

Page 45: ...End 50 10 Nominal Trace Space within LPC Signal Group 3H Spacing to Other Signal Group 3H LA Please see the SOM 5992 Layout Checklist LB Carrier Board Length Max length of LA LB 8 5 Single source Leng...

Page 46: ...le 14 below defines the port pin mapping for the I O expander There are two pairs of PHY strapping signals defined The first pair is designated as 10G_PHY_CAP_01 and 10G_PHY_CAP_23 These are actual CO...

Page 47: ...C43 10GBASE KR port receive input differential pairs Module has integrated AC Coupling Capacitor Carrier board N C if not used N C if not used I KR 10G_KR_TX2 10G_KR_TX2 D29 D30 10GBASE KR port trans...

Page 48: ...between the MAC and an external PHY Carrier board Device Connect to PHY circuit N C if not used OC MOS 3 3V Suspend 3 3V I2C Mode I2C Clock signal of the 2 wire management interface used for serial da...

Page 49: ...ween the MAC and an external PHY Carrier board Device Connect to PHY circuit N C if not used OC MOS 3 3V Suspend 3 3V 1 I2C Mode I2C data signal of the 2 wire management interface used for serial data...

Page 50: ...etween the MAC and an external PHY Carrier board Device Connect to PHY circuit N C if not used OC MOS 3 3V Suspend 3 3V 1 I2C Mode I2C Clock signal of the 2 wire management interface used for serial d...

Page 51: ...10GbE controller to access the management registers of an external Optical SFP Module Carrier board I O OD CMOS 3 3V Suspend 3 3V 10G_SFP_SCL0 D39 I2C clock signal of the 2 wire management interface u...

Page 52: ...s of an external Optical SFP Module Carrier board I O OD CMOS 3 3V Suspend 3 3V 1 10G_SFP_SCL3 D32 I2C clock signal of the 2 wire management interface used by the 10GbE controller to access the manage...

Page 53: ...such as a 1pps signal See section 2 6 2 for details I O CMOS 3 3V Suspend 3 3V 10G_SDP1 D40 Software Definable Pins Can also be used for IEEE1588 support such as a 1pps signal See section 2 6 2 for d...

Page 54: ..._KR_LED1_1 PHY 1 LED 1 LINK SPEED MAX P0_5 10G_KR_LED1_2 PHY 1 LED 2 LINK SPEED P0_6 0G_KR_STRAP01 PHY 0 1 0 PHY to use I2C 1 PHY to use MDIO P0_7 10G_KR_STRAP23 PHY 2 3 0 PHY to use I2C 1 PHY to use...

Page 55: ...2 5 2 Example 10 GB Ethernet Designs 2 5 2 1 2016 Silicon 10GbE Fiber Implementation Figure 8 10G Ethernet Design for Fiber PHY with Broadwell DE...

Page 56: ...2 5 2 2 2016 Silicon 10GbE Copper Implementation Figure 9 10G Ethernet Design for Copper PHY with Broadwell DE...

Page 57: ...2 5 2 3 Future Silicon 10GbE Fiber Implementation Figure 10 10G Ethernet Design for Fiber PHY with Future SoC...

Page 58: ...2 5 2 4 Future Silicon 10GbE Copper Implementation Figure 11 10G Ethernet Design for Copper PHY with Future SoC...

Page 59: ...uation B Direct attached module to module connection Coupling is at receiver in this case on both modules at receive pair No coupling on carrier Figure 13 10G Ethernet AC coupling direct cable Situati...

Page 60: ...normative channel specification as stated in IEEE 802 3 Annex 69B Simulations have shown that the trace length allocations in Table15 meet the required channel specifications Proper high speed design...

Page 61: ...erred Min 40 mil trace edge to major plane edge spacing GND stitching vias required next to signal vias if transitioning layers between GND layers Power referencing acceptable if stitching caps are us...

Page 62: ...nd 50 10 Nominal Trace Space within CRT DAC Signal Group Min 10mils Spacing to Other Signal Group Min 10mils LA Please reference SOM 5992 Layout check list LB Carrier Board Length Max length of LA LB...

Page 63: ...d The corresponding LAN differential pair and control signals can be found on rows A and B of the Module s connector Table 18 Gb Ethernet Interface Signal Descriptions Signal Pin Description I O Note...

Page 64: ...troller 0 100Mbit sec link indicator active low Carrier Board N C if not used O 3 3V Suspend 3 3V OD CMOS GBE0_LINK1000 A5 Ethernet controller 0 1000Mbit sec link indicator active low Carrier Board N...

Page 65: ...e module carrier interface Software can configure the NIC to output a PPS signal onto this pin that connects it to one or more elements on the module and or carrier board Example2 The carrier board ha...

Page 66: ...hich the Ethernet target device is implemented on the Carrier Board for instance an Ethernet switch may add the insertion loss for the RJ45 Ethernet jack and integrated magnetics to the Carrier Board...

Page 67: ...00mils Spacing between differential pairs and low speed non periodic signals Min 100mils Spacing between digital ground and analog ground plane between the magnetics Module and RJ45 connector Min 60mi...

Page 68: ...45 connector housing The analog ground plane should be coupled to the carrier s digital logic ground plane using a capacitive coupling circuit that meets the ground plane isolation requirements defin...

Page 69: ...designer s discretion All other USB ports if implemented shall be host ports USB Port 0 data or D USB Port 0 data or D Carrier board Device Connect to D Conn Connect 90 100MHz Common Choke in series...

Page 70: ...nect to Overcurrent of Power Distribution Switch and Bypass 0 1uF to GND N C if not used I 3 3V SUSPEND 3 3V CMOS USB_2_3_OC A44 USB over current sense USB channels 0 and 1 A pull up for this line sha...

Page 71: ...where highly capacitive loads are employed Transient faults are internally filtered Additionally they offer a fault status output that is asserted during over current and thermal shutdown conditions...

Page 72: ...implementations in which the USB target device is implemented on the Carrier Board may add the ferrite and USB connector insertion loss values to the Carrier Board budget The Carrier Board insertion l...

Page 73: ...res and also helps prevent free radiation of the signal from the edge of the PCB Avoid stubs on high speed USB signals because stubs cause signal reflections and affect signal quality If a stub is una...

Page 74: ...se attenuation A design should include a common mode choke footprint to provide a stuffing option in the event the choke is needed to pass EMI testing Below figure shows the schematic of a typical com...

Page 75: ...ough testing Thorough testing means that the signal quality must be checked for low speed full speed and highspeed USB operation Further common mode choke information can be found on the high speed US...

Page 76: ...pacing between differential pairs and high speed periodic signals Min 50 mils Spacing between differential pairs and low speed non periodic signals 7H MS and 5H DS 1 LA Please see the SOM 5992 Layout...

Page 77: ...in a USB 3 0 Type A receptacle but the USB 3 0 SuperSpeed functions will not be available 2 8 1 USB3 0 Signal Definitions Table 24 USB3 0 Signal Definitions Signal Pin Description I O Note USB_SSTX0 U...

Page 78: ...odule has integrated AC Coupling Capacitors Carrier Board Device Connect to StdA_SSRX Conn Connect 0 and 90 100MHz USB3 0 Common Mode Choke NL combined in series and USB3 0 ESD suppressors to GND to P...

Page 79: ...r Board Device Connect AC Coupling Capacitors 100nF near COME to StdA_SSTX Conn Connect 0 and 90 100MHz USB3 0 Common Mode Choke NL combined in series and USB3 0 ESD suppressors to GND to Pin 6 StdA_S...

Page 80: ...tputs should be connected to the corresponding COM Express Modules USB over current sense signals Fault status signaling is an option at the USB specification If you don t need the popup message in yo...

Page 81: ...2 USB3 0 Insertion Loss Budget Table 25 USB3 0 Insertion Loss Budget Segment Loss dB Notes LA 1 94 Up to 3 inches of Module trace 2 5 GHz LB 1 20 COM Express connector at 2 5 GHz LC 3 64 Up to 5 inche...

Page 82: ...eed periodic signals 11H MS and 7H DS 1 Spacing between differential pairs and low speed non periodic signals 11H MS and 7H DS 1 LA Please see the SOM 5992 Layout Checklist LB Carrier Board Length Max...

Page 83: ...eet these needs The eSATA connector does not have the L shaped key and because of this SATA and eSATA cables cannot be interchanged 2 9 1 SATA Signal Definitions Table 27 SATA Signal Definitions Signa...

Page 84: ...not used I O 3 3V CMOS Able to drive 10 mA Notes 2 9 2 SATA Routing Guidelines SATA Insertion Loss Budget The Serial ATA source specification provides insertion loss figures only for the SATA cable Th...

Page 85: ...se effects of EMI and signal quality performance caused by reference plane change Stitching capacitors are smallvalued capacitors 1 F or lower in value that bridge the power and ground planes close to...

Page 86: ...ngth mismatch must not be more than 20 mils 0 508 mm Examples of segments might include breakout areas routes running between two vias routes between an AC coupling capacitor and a connector pin etc T...

Page 87: ...fferential pairs and high speed periodic signals 9H MS and 7H DS 1 Spacing between differential pairs and low speed non periodic signals 9H MS and 7H DS 1 LA Please see the SOM 5992 Layout Checklist L...

Page 88: ...terface against accidental exposure to 3 3V Module LPC signals In both cases a simple and low cost protection scheme may be realized with low value in line series resistors typically 33 ohms and BAT54...

Page 89: ...C if not used I O 3 3V CMOS ESPI_IO_0 ESPI_IO_1 ESPI_IO_2 ESPI_IO_3 ESPI Mode eSPI Master Data Input Outputs These are bi directional input output pins used to transfer data between master and slaves...

Page 90: ...oat this line or pull it low Carrier Board Connect to N C LPC mode GND eSPI mode I NA CMOS 2 LPC_CLK B10 LPC clock output 24MHz Carrier Board Connect to LPC LCLK N C if not used O 3 3V CMOS ESPI_CK ES...

Page 91: ...e EMI The LPC clock implementation should follow the routing guidelines for the PCI clock defined in the COM Express specification and the PCI Local Bus Specification Revision 2 3 2 10 2 3 Carrier Boa...

Page 92: ...at 50 Ohms Carrier routed SPI traces shall have 5 mil via to via clearance 4 mil trace to via clearance and 10 mil clearance to any other traces The Carrier shall have a 33 Ohm series termination betw...

Page 93: ...nal Trace Space within LPC Signal Group Min 15mils Spacing to Other Signal Group Min 15mils LA Please see the SOM 5992 Layout Checklist LB Carrier Board Length Max length of LA LB 23 Length matching b...

Page 94: ...hip select for Carrier Board SPI may be sourced from chipset SPI0 or SPI1 Carrier Board Connect to SPI flash pin 1 Chip Select N C if not used O CMOS 3 3V Suspend or 3 3V S0 1 8V Suspend or 1 8V S0 SP...

Page 95: ...r to Table X BIOS Selection Straps Carrier Board 1 N C 0 PD 1K to GND I CMOS BIOS_DIS1 B88 Selection strap to determine the BIOS boot device The Carrier should only float these or pull them low please...

Page 96: ...f level shifters Module designs that implement a 1 8V Carrier SPI interface should protect themselves against possible exposure to 3 3V Carrier SPI signals Carrier designs that implement a 1 8V SPI in...

Page 97: ...CS0 The first two regions the Descriptor and the BIOS are mandatory The other regions are optional The regions may all be packed into the same SPI device or may be divided between more than one SPI de...

Page 98: ...sh being attached behind a board Management Controller BMC or Embedded Controller EC MAFS and SAFS configurations apply to both LPC and eSPI enabled configurations Refer to Figure27 BIOS Selection LPC...

Page 99: ...High Not used was FWH 1 1 1 SPI 0 Module Module High Module A MAFS on Module LPC bus enabled 0 0 0 SPI 0 Carrier Module SPI1 Module C MAFS on Module ESPI bus enabled 0 0 1 SPI 0 Module Carrier SPI0 C...

Page 100: ...ECs SIOs etc but the BIOS boot path is on the SPI bus eSPI BIOS SAFS Considerations eSPI Enabled In an eSPI enabled SAFS system the SPI boot device is located on the far side of a BMC or EC The syste...

Page 101: ...es Notes Signal Group SPI Single End 50 10 Nominal Trace Space within SPI Signal Group Min 10mils Spacing to Other Signal Group Min 10mils LA Please see the SOM 5992 Layout Checklist LB Carrier Board...

Page 102: ...ossible leakage issue that can arise when using a R3 x Module with a R2 1 Carrier that supports I2C devices The R2 1 Carrier will power any I2C devices from the non standby power rail A R3 x Module wi...

Page 103: ...Connect an 5V isolation circuit controlled by COME pin B24 PWR_OK to SCL of I2C device N C if not used I O OD CMOS 3 3V Suspend 3 3V I2C_DAT B34 General Purpose I2C data I O line Carrier Board 3 3VSB...

Page 104: ...ength of LA LB ASPA Length Mismatch NA Via Usage Try to minimize number of vias Notes 2 12 4 Connectivity Considerations The maximum amount of capacitance allowed on the Carrier General Purpose I2C bu...

Page 105: ...evices on the Carrier Board using the SMBus are normally powered by the 3 3V main power To avoid current leakage between the main power of the Carrier Board and the Suspend power of the Module the SMB...

Page 106: ...n B24 PWR_OK to SMBCLK of SMBus device N C if not used I O OD CMOS 3 3V Suspend 3 3V SMB_DAT B14 System Management bidirectional data line Carrier Board 3 3VSB SMBus device Connect to SMBDAT of SMBus...

Page 107: ...st of SMBus addresses used on the Module Do not use the same address for Carrier located devices 2 13 3 SMB Trace Length Guidelines Figure 32 Topology for SMB Table 38 SMB Trace Length Guidelines Para...

Page 108: ...ld not be implemented as USB peripherals as such implementations are generally not useful for low level debug purposes 2 14 1 Serial interface Signal Definitions Table 39 Serial interface Signal Defin...

Page 109: ...Trace Length Guidelines Parameter Main Route Guidelines Notes Signal Group Serial interface Single End 50 15 Nominal Trace Space within SPI Signal Group Min 10mils Spacing to Other Signal Group Min 15...

Page 110: ...e Carrier Board CAN transceiver is carried on Module line SER1_TX Data from the Carrier Board CAN transceiver to the COM Express Module based CAN controller is carried on Module line SER1_RX The Carri...

Page 111: ...for further details on termination 2 15 3 CAN interface Trace Length Guidelines Figure 34 Topology for CAN interface Table 42 CAN interface Trace Length Guidelines Parameter Main Route Guidelines Note...

Page 112: ...e pin out type is detected O 5V PDS Only Available on T2 T6 1 TYPE0 is GND pin 2 TYPE1 is NC pin 3 TYPE2 is GND pin TYPE10 A97 Indicates to the Carrier Board that a Type 10 Module is installed Indicat...

Page 113: ...the Pulse Width Modulation PWM technique to control the fan s RPM Carrier Board R2 R3 Module only PD 4 7K to GND and connects to FAN connector pin 2 PWMOUT via Smart FAN circuit N C if not used O 3 3V...

Page 114: ...ect to GPO 3 0 N C if not used O 3 3V CMOS 1 GPI0 SDIO_DAT0 GPI1 SDIO_DAT1 GPI2 SDIO_DAT2 GPI3 SDIO_DAT3 A54 A63 A67 A85 General Purpose Input for system specific usage The signals are pulled up by th...

Page 115: ...sponse This signal is used for card initialization and for command transfers During initialization mode this signal is open drain During command transfer this signal is in push pull mode Carrier Board...

Page 116: ...ated after the Module enters S0 unless there is a power fail condition Signals SUS_S3 SUS_S4 and SUS_S5 define the signaling to indicate that the Module has entered the ACPI power saving mode S3 Suspe...

Page 117: ...dicates imminent suspend operation used to notify LPC devices Not used in eSPI implementations Carrier Board Connect to LPCPD of LPC device N C if not used O 3 3V Suspend CMOS SUS_S3 A15 Indicates sys...

Page 118: ...n B11 of PCIE slot N C if not used I 3 3V Suspend CMOS WAKE1 B67 General purpose wake up signal Carrier Board Connect to PME of SIO N C if not use I 3 3V Suspend CMOS BATLOW A27 In a type 7 system BAT...

Page 119: ...cification to be met with a 1 ohm discharge resistance The Module design should prevent overheating or damage to any Module circuitry in the event that RAPID_SHUTDOWN is asserted without the removal o...

Page 120: ...gnal can be used to initiate thermal throttling Carrier Board Connect to THRM output of Hardware Monitor N C if not used I 3 3V CMOS THRMTRIP A35 Thermal Trip indicates an overheating condition of the...

Page 121: ...ta CD Minimum Trace Spacing Between Other SD Card and Interface Signals 5 mils 1 Main Route segment for CLK Minimum Trace Spacing Between Other SD Card and Interface Signals 15mils 1 Spacing to Other...

Page 122: ...0 Reserved pin RSVD A32 Reserved pin RSVD A33 Reserved pin RSVD A48 Reserved pin RSVD A86 Reserved pin RSVD A87 Reserved pin RSVD B28 Reserved pin RSVD B29 Reserved pin RSVD B30 Reserved pin RSVD C63...

Page 123: ...ided to the Module If Suspend functions are not used the Module VCC_5V_SBY pins should be left open On some Modules there may be a slight power efficiency advantage to connecting the Module VCC_5V_SBY...

Page 124: ...Me PWR_BTN To COMe Or other wake event G3 T1 S5 S0 SUS_S3 From COMe PSON To ATX PS VCC_12V To COMe 10 95 T2 VCC_5V VCC3V For Carrier Board use not needed by Module T3 PWR_OK To COMe T4 Module Intermal...

Page 125: ..._3V output 500ms T3 VCC_12V rise time from 10 to 95 0 1ms 20ms T4 PWR_OK delay 100ms T5 PWR_OK rise time 10ms T6 See Note 1 T7 Power down warning 1ms VCC_5V_SBY To COMe Optional PWR_BTN To COMe Option...

Page 126: ...wer rail Almost all such signals are active low Such signals if used should be driven low by open drain Carrier Board circuits to assert them Pull ups if present should be high value 10K to 100K and t...

Page 127: ...rom starting before Carrier Board devices are ready One method to achieve this is to delay assertion of the PWR_OK signal to the Module until the Carrier Board initialization process has completed Not...

Page 128: ...DC Current Characteristics1 Intel D 1548 2 0GHz PTU Power Plane Maximum Power Consumption Symbol S0 S3 S5 G3 VIN 12V 55 53W VIN 8 5V 52 82W VIN 20V 54 97W V5SB_CB 0 045W W 1 761W RTC Battery 1 48uA 4...

Page 129: ...4 3 Inrush Current Table 54 Inrush Current Power Plane Maximum Symbol G3 to S5 S5 to S0 V5SB_CB 1 2708A VIN 12V 2 54070A VIN 8 5V 3 2156A VIN 20V 1 7559A...

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