Advantech SOM-5883, User Manual

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33 SOM-5883 User Manual
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3.4.5 Intel(R) Time Coordinated Computing
Figure 3.14 Intel(R) Time Coordinated Computing

#AC Split Lock
Enable or Disable Alignment Check Exception (#AC). When enabled, this will
assert an #AC when any atomic operation has an operand that crosses two
cache lines.

IFU Enable
Enable or Disable Instruction Fetch Unit(IFU). When enabled, Instructions will
be prefetch to the cache.

Intel(R) TCC Authentication Menu
Intel(R) TCC Authentication Menu options.

Intel(R) TCC Mode
Enable or Disable Intel(R) TCC Mode. When enabled, this will modify system
settings to improve real-time performance. The full list of settings and their cur -
rent state are displayed below when Intel(R) TCC mode is enabled.

IO Fabric Low Latency
Enable or Disable IO Fabric Low Latency. This will turn off some power manage -
ment in the PCH IO fabrics. This option provides the most aggressive IO Fabric
performance setting. S3 state is NOT supported.

OPIO Recentering
Enable or Disable Opio Recentering to improve Pcie latency.

C states
Enable/Disable CPU Power Management. Allows CPU to go to C states when
it's not 100% utilized.

Intel(R) Speed Shift Technology
Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose
the CPPC v2 interface to allow for hardware controlled P-states.