Advantech SOM-Express Design Guide
Chapter 5 Carrier Board Design Guidelines
45
Table 5.7 PCI Data Signals Routing Summary
Trace
Impedance
PCI Routing Requirements
Topology
Maximum Trace Length
(unit: inch)
L1 L2 L3 L4
2 Slots
W1 = W2 = 0.5
inches,
R_IDSEL = 300
to 900.
10 1.0
3 Slots
W1 = W2 = 0.5
inches,
R_IDSEL = 300
to 900.
10 1.0 1.0
55
Ω
+/- 10%
6 mils width, 6 mils spacing (based
on stackup assumptions)
4 Slots
W1 = W2 = 0.5
inches,
R_IDSEL = 300
to 900.
10 1.1 1.1 1.1
5.1.3.2 PCI Clock Layout Example
PCI slot 1
or Device 1
PCI slot 2
or Device 2
PCI slot 3
or Device 3
PCI slot 4
or Device
4
PCI_CLK
Clock
Gen
SOM-
Express
SOM-
Express
On Board
Chipset
W1
W2
W4
R1
R2
W5
Conne
cto
r
Clock
Buf
fe
r
Carrier
board
W3
Figure 5-4 PCI Clock Layout Example
Table 5.8 PCI Clock Signals Routing Summary
Trace
Impedance
PCI Routing Requirements
Topology
Maximum trace
Length
Damping
Resistor
55
Ω
+/- 10%
6 mils width, 50 mils spacing (based on
stackup assumptions)
2 ~ 4
Devices
W1: 0.5 inch
W2: 5 inches
W3: 15 inches
W4: 0.5 inch
W5: as long as
needed
R1: 33
Ω
R2: 33
Ω
Note:
Clock skew between PCI slots/devices should be less than 2 ns@33 MHz and 1
ns@66 MHz. The recommended value of the clock trace tolerance of W3 (a,b,c,d) is
5 inches (Max).
