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Your ePlatform Partner 

  User’s Manual for Advantech SOM-A2552 series module V1.00 

                                                  

 

 

22 

116 

UART2_CTS 

I  UART2 Clear-to-Send signal pin. If 

user doesn’t need UART2 function, 
user could use this pin as GPIO. 
The pin connects to SoC PXA255 
GPIO44. 

Pull high with 
100Kohm 

117 

UART3_TXD 

O  UART3 Transmit signal pin. If user 

doesn’t need UART3 function, user 
could use this pin as GPIO. The 
pin connects to SoC PXA255 
GPIO47. 

Pull high with 
100Kohm 

118 

UART2_DTR 

O  UART Data-Terminal-Ready signal 

pin. 

Pull high with 
100Kohm 

119 

UART3_CTS 

I  UART3 Clear-to-Send signal pin.  Pull high with 

100Kohm 

120 

UART2_RI 

I  UART2 Ring Indicator signal pin. 

Pull high with 
100Kohm 

121 

UART3_DTR 

O  UART3 Data-Terminal-Ready 

signal pin. 

Pull high with 
100Kohm 

122 

UART3_RI 

I  UART3 Ring Indicator signal pin. 

Pull high with 
100Kohm 

123 

UART1_DSR 

I  UART1 Data-Set-Ready signal pin. Pull high with 

100Kohm 

124 

UART1_DCD 

I  UART1 Data-Carrier-Detect signal 

pin. 

Pull high with 
100Kohm 

125 

UART1_CTS 

I  UART1 Clear-to-Send signal pin.  Pull high with 

100Kohm 

126 

UART1_RXD 

I  UART1 Receive signal pin. 

Pull high with 
100Kohm 

127 

UART1_RTS 

O  UART1 Request-to-Send signal 

pin. 

Pull high with 
100Kohm 

128 

UART1_TXD 

O  UART1 Transmit signal pin. 

Pull high with 
100Kohm 

129 

UART1_DTR 

O  UART1 Data-Terminal-Ready 

signal pin. 

Pull high with 
100Kohm 

130 

GND 

P  Ground 

- 

131 

UART1_RI 

I  UART Ring Indicator signal pin. 

Pull high with 
100Kohm 

132 

N.C. 

-  N.C. just float this pin. 

- 

133 

N.C. 

-  N.C. just float this pin. 

- 

134 

N.C. 

-  N.C. just float this pin. 

- 

135 

N.C. 

-  N.C. just float this pin. 

- 

136 

GND 

P  Ground 

- 

137 

VDD_ENA 

O  LCD power control signal. User 

can use this pin to control the LCD 
logic power MOS switch to achieve 
power-saving.   

No pulling 

138 

N.C. 

-  N.C. just float this pin. 

- 

139 

VEE_ENA 

O  STN LCD VEE power control 

signal. User can use this pin to 

No pulling 

Summary of Contents for RISC Module SOM-A2552

Page 1: ...vantech RISC SOM A2552 Series Module System Module with Intel XScale PXA255 processor SMI SM501 Graphic chip with Windows CE NET Released Version V1 00 Released Date May 19 2004 Advantech Co Ltd Risc Embedded Computing Division http www advantech com risc Your ePlatform Partner ...

Page 2: ...third parties that may result from such use Acknowledgements IBM PC AT PS 2 and VGA are trademarks of International Business Machines Corporation Intel is trademark of Intel Corporation Microsoft Windows CE NET is a registered trademark of Microsoft Corp All other product names or trademarks are properties of their respective owners For more information on this and other Advantech products please ...

Page 3: ...Platform Partner User s Manual for Advantech SOM A2552 series module V1 00 3 Revision History Version Date Reason V1 00 2004 05 19 1st Official released version For 9696255201 9696255801 9696255F01 9696255F12 ...

Page 4: ...attery powered great heavy display base embedded Internet appliance or so called smart embedded devices SOM A2552 series Design highlight WinCE NET ready platform as functional system engine SoC Intel XScale PXA255 Companion Graphic Chip SMI SM501provide complete SBC functionality high performance Graphic function in a module Pre define I O Ready bus thru SODIMM 200 interface Design in package Ref...

Page 5: ... obsolescence as computer technology continues to evolve A properly designed SOM A2552 CSB can be used with several successive generations of SOM A2552 modules An SOM A2552 CSB design thus has many of the advantages of a custom computer board design but delivers better obsolescence protection greatly reduced engineering effort and faster time to market Based embedded platform integrates both low l...

Page 6: ...M A255x means SOM A2552 SOM A2558 and SOM A2552 l 64MB compact flash card the CF card is empty without any file inside l SOM A255x series support CD includes sample image boot loader manuals datasheets SOM A255x series CSB design guide S W utility upgrade utility testing utility SOM A255x series WinCE 4 2 BSP SDK Application note l Testing Set It is designed for sample CSB or user own CSB mass pro...

Page 7: ...em 6 4 TFT VGA LCD kit The kit includes 6 4 TFT VGA LCD kit PRIMEVIEW PD064VT2 4 wires resistive T S inverter cables and installation guide All SOM A255x series support this LCD kit in reference image l LCD A104 TTS1 0 Optional item 10 4 TFT SVGA LCD kit The kit includes 10 4 TFT SVGA LCD AUO G104SN03v2 4 wires resistive T S inverter cables and installation guide Only SOM A255F SOM A2552 series ca...

Page 8: ...em utility tool suit for developers easily and simply develop validate and upgrade their own SW platform solution CE Tuner helps users fine tune their target SW image for optimized performance verify settings and platform tests before the production image is certified RISC CE Builder is not included in Design in kit If you need more information about it please contact with ae risc advanch com tw o...

Page 9: ... Full H W flow control SPI and enhanced SSP USB end point interface and MMC SD Card Support for expandable memory and I O functionality About Intel PXA255 SoC detail information user could visit Intel web site for more Enhance Graphic Chip SMI SM501 introduction The SM501 is a Mobile System on a Chip MSOC device This robust device delivers high performance video and 2D operation providing a soluti...

Page 10: ...ation Option CPU PXA255 400MHz 200 300 400 MHz Graphic Chip SMI SM501 with 8MB embedded SDRAM SM501 with without 8MB embedded SDRAM System Memory SDRAM 64MB 16 32 64 128 MB Booting Flash 1MB NOR Flash On board Flash Image Storage 0MB 0 16 32 64MB OS Image Storage WinCE NET Linux By customer request AMI Bus X1 Bus 100 pin B2B connector with driving buffers Yes Feature Extension Bus X2 Bus 100 pin B...

Page 11: ...oesn t fit user s requirement user could contact with Advantech for SOM A2552 reconfiguration Advantech SOM A255x series have wide temperature products About detail product information user could visit website http www advantech com tw epc phoenix User also could contact with ae risc advanch com tw or advantech regional sales for further information SOM A2552 440B0 is off the shelf standard produc...

Page 12: ...ut procedure user could follow the 1st drawing to place the connector SOM A2552 series PCB form factor is 68mm 68mm 68mm The 2nd drawing shows the PCB thickness limitation The component side height is 2 8mm and the solder side maximum height is 3 00mm and the PCB thickness is 1 00mm The 3rd drawing shows allied mechanical data of SOM A2552 series board and CSB Users could see that the matting heig...

Page 13: ...Operating Conditions VIH Input High Voltage all standard input and I O pins 0 8 VCC VCC VIL Input Low Voltage all standard input and I O pins VSS 0 2 VCC Output DC Operating Conditions VOH Output High Voltage all standard output and I O pins VCC 0 1 VCC VOL Output Low Voltage all standard output and I O pins VSS VSS 0 4 1 2 3 Power Consumption In WinCE O S environment SOM A2552 series products hav...

Page 14: ...2 series module V1 00 14 Chapter 2 Assignments and Descriptions 2 1 Connector Locations Figure SOM A2552 series component side Figure SOM A2552 series solder side SOM Connector vendor table Connector vendor PN AMI bus X1 Matsushita electric works LTD AXK600335 ...

Page 15: ...ddress lines data lines GPIOs for interrupt source and Chip select pins nCS Users could use this bus to extend any other IC controller on CSB to implement the function which SOM modules not provide In order to keep the system bus signals well every address lines and data lines are driven by buffers Buffers signals direction controls are implemented by CPLD X2 SODIMM 200 connector Most I O function...

Page 16: ...No pulling 6 SA_SKT_D10 IO PCMCIA CF data 10 No pulling 7 SA_SKT_D3 IO PCMCIA CF data 3 No pulling 8 SA_SKT_D11 IO PCMCIA CF data 11 No pulling 9 SA_SKT_D4 IO PCMCIA CF data 4 No pulling 10 SA_SKT_D12 IO PCMCIA CF data 12 No pulling 11 SA_SKT_D5 IO PCMCIA CF data 5 No pulling 12 SA_SKT_D13 IO PCMCIA CF data 13 No pulling 13 SA_SKT_D6 IO PCMCIA CF data 6 No pulling 14 SA_SKT_D14 IO PCMCIA CF data 1...

Page 17: ...rom PCMCIA I O space No pulling 41 SA_SKT_A24 IO PCMCIA CF address 24 No pulling 42 XP AI 4 wires resistive touch screen signals X Position Input No pulling 43 nSA_SKT_WE O PCMCIA write enable output Performs writes to PCMCIA memory and to PCMCIA attribute space Also used as the write enable signal for Variable Latency I O No pulling 44 YP AI 4 wires resistive touch screen signals Y Position Input...

Page 18: ...S 1 I PCMCIA CF slot 1 voltage sense pin 1 Pull high with 10Kohm 68 nSA_SKT0_CE 2 O PCMCIA CF slot 0 card enable pin 2 No pulling 69 SA_SKT1_RDY I PCMCIA CF slot 1 ready pin Pull high with 10Kohm 70 SA_SKT0_RDY I PCMCIA CF slot 0 ready pin Pull high with 10Kohm 71 nSA_SKT0_VS 2 I PCMCIA CF slot 0 voltage sense pin 2 Pull high with 10Kohm 72 nSA_SKT1_VS 2 I PCMCIA CF slot 1 voltage sense pin 2 Pull...

Page 19: ...inimum assertion time for nBATT_FAULT is 1 ms Pull high with 100Kohm 84 nSW_RESET I System software reset input pin Falling edge triggered Pull high with 10Kohm 85 nVDD_FALT I VDD Fault Signals that the main power source is going out of regulation nVDD_FAULT causes the PXA255 processor to enter sleep mode or force an Imprecise Data Exception which cannot be masked nVDD_FAULT is ignored after a wak...

Page 20: ... connects to SoC PXA255 GPIO16 Pull low with 1Kohm 92 SYS_VCC P SOM system DC power 5V input pin SYS_VCC should always be powered by DC 5V even in sleep mode 93 SYS_VCC3P3 P SOM system DC power 3 3V input pin SYS_VCC should always be powered by DC 3 3V even in sleep mode 94 SYS_VCC P SOM system DC power 5V input pin SYS_VCC should always be powered by DC 5V even in sleep mode 95 SYS_VCC3P3 P SOM s...

Page 21: ...ld use this pin as GPIO The pin connects to SoC PXA255 GPIO45 Pull high with 100Kohm 107 GND P Ground 108 UART2_DCD I UART2 data Carrier Detect signal pin Pull high with 100Kohm 109 UART3_DCD I UART3 data Carrier Detect signal pin Pull high with 100Kohm 110 UART2_DSR I UART2 Data Set Ready signal pin Pull high with 100Kohm 111 UART3_DSR I UART3 Data Set Ready signal pin Pull high with 100Kohm 112 ...

Page 22: ...100Kohm 123 UART1_DSR I UART1 Data Set Ready signal pin Pull high with 100Kohm 124 UART1_DCD I UART1 Data Carrier Detect signal pin Pull high with 100Kohm 125 UART1_CTS I UART1 Clear to Send signal pin Pull high with 100Kohm 126 UART1_RXD I UART1 Receive signal pin Pull high with 100Kohm 127 UART1_RTS O UART1 Request to Send signal pin Pull high with 100Kohm 128 UART1_TXD O UART1 Transmit signal p...

Page 23: ...high with 100Kohm 152 UART5_TXD O UART5 Transmit signal pin Pull high with 100Kohm 153 N C N C just float this pin 154 N C N C just float this pin 155 N C N C just float this pin 156 N C N C just float this pin 157 nVBRIR_INC O One of LCD inverter backlight brightness control signals nVBRIR_INC is used to increase or decrease Wiper Control Advantech suggests to connect the pin to DS1804 1st pin No...

Page 24: ...ling 172 B2 O B in 24 bit TFT mode No pulling 173 B3 O B in 24 bit TFT mode No pulling 174 B4 O B in 24 bit TFT mode No pulling 175 B5 O B in 24 bit TFT mode No pulling 176 B6 O B in 24 bit TFT mode No pulling 177 B7 O B in 24 bit TFT mode No pulling 178 G0 O G in 24 bit TFT mode No pulling 179 G1 O G in 24 bit TFT mode No pulling 180 G2 O G in 24 bit TFT mode No pulling 181 G3 O G in 24 bit TFT m...

Page 25: ...ound 199 M_DE O Flat Panel Display Enable This signal is used as a data enable when the pixel clock needs to latch pixel data No pulling 200 SHCLK O Flat Panel Pixel Clock The active edge of FPCLK is programmable The LCD panel uses this clock when loading pixel data into its Line Shift register This signal connects to the TXCLK input of the LVDS transmitter No pulling 100 pin B2B connector Pin Out...

Page 26: ...lling B9 GND P Ground A9 BUF_RDY I Variable Latency I O Ready pin Notifies the memory controller when an external bus device is ready to transfer data Pull high with 100Kohm B10 DATA15 IO SoC PXA255 system data 15 No pulling A10 DATA14 IO SoC PXA255 system data 14 No pulling B11 DATA13 IO SoC PXA255 system data 13 No pulling A11 DATA12 IO SoC PXA255 system data 12 No pulling B12 DATA11 IO SoC PXA2...

Page 27: ... in the memory controller The memory controller also provides control register bits for clock division and deassertion of each SDCLK pin SDCLK 2 1 control register assertion bits are always deasserted upon reset No pulling A21 BUF_SDCKE 1 O SDRAM and or Synchronous Static Memory clock enable Connect to the clock enable pins of SDRAM It is deasserted during sleep BUF_SDCKE1 is always deasserted upo...

Page 28: ...PXA255 system data 22 No pulling B37 DATA23 IO SoC PXA255 system data 23 No pulling A37 nBUF_SDCA S O SDRAM CAS Connect to the column address strobe CAS pins for all banks of SDRAM No pulling B38 nBUF_SDCS 2 O SDRAM CS for banks 2 Connect to the chip select CS pins for SDRAM For the PXA255 processor nSDCS0 can be Hi Z Nsdcs1 3 cannot No pulling A38 BUF_DQM1 O SDRAM DQM for data bytes 1 Connect to ...

Page 29: ...IRQ function The pin is not available for CSB design of SOM A2558 SOM A255F platform SOM A2558 SOM A255F user must float this pin This pin is directly connected to SoC PXA255 GPIO9 F12 A42 C950_485_IR Q I Advantech default function is used as external 16C950 solution IC IRQ The pin directly connects to PXA255 GPIO10 F7 pin If user doesn t design 16C950 on CSB to expand COM function user could use ...

Page 30: ...46 nBUF_CS1 O Static chip selects Chip selects to static memory devices such as ROM and Flash Individually programmable in the memory configuration registers nBUF_CS1 can be used with variable latency I O devices Advantech default uses this pin as storage flash chip select pin If no special application Advantech strongly suggest user to open this pin in CSB Pull high with 100Kohm B47 nBUF_CS4 O St...

Page 31: ...ign a controller in CSB with DMA mode please check with ae risc advantech com tw first If use doesn t want to use this pin as DMA_REQ use could use the pin as GPIO The pin connects to SoC PXA255 GPIO19 Pull low with 1Kohm B49 MBREQ I Memory Controller alternate bus master request Allows an external device to request the system bus from the Memory Controller If user wants to design a controller in ...

Page 32: ...t float this pin A1 N C N C just float this pin B2 N C N C just float this pin A2 N C N C just float this pin B3 N C N C just float this pin A3 N C N C just float this pin B4 N C N C just float this pin A4 N C N C just float this pin B5 N C N C just float this pin A5 N C N C just float this pin B6 N C N C just float this pin A6 N C N C just float this pin B7 N C N C just float this pin A7 N C N C ...

Page 33: ...s pin B26 N C N C just float this pin A26 N C N C just float this pin B27 N C N C just float this pin A27 N C N C just float this pin B28 N C N C just float this pin A28 N C N C just float this pin B29 N C N C just float this pin A29 N C N C just float this pin B30 N C N C just float this pin A30 N C N C just float this pin B31 N C N C just float this pin A31 N C N C just float this pin B32 N C N ...

Page 34: ...put for RGB 5 6 5 mode or Y 6 video pixel input for YUV 4 2 2 mode No pulling B41 ZV13 I 16 bit R 2 video pixel input for RGB 5 6 5 mode or Y 5 video pixel input for YUV 4 2 2 mode No pulling A41 ZV12 I 16 bit R 1 video pixel input for RGB 5 6 5 mode or Y 4 video pixel input for YUV 4 2 2 mode No pulling B42 ZV11 I 16 bit R 0 video pixel input for RGB 5 6 5 mode or Y 3 video pixel input for YUV 4 ...

Page 35: ...it B 2 video pixel input for RGB 5 6 5 mode U 2 video pixel input for YUV 4 2 2 mode or V 2 video pixel input for YUV 4 2 2 mode No pulling B47 ZV1 I 16 bit B 1 video pixel input for RGB 5 6 5 mode U 1 video pixel input for YUV 4 2 2 mode or V 1 video pixel input for YUV 4 2 2 mode No pulling A47 ZV0 I 16 bit B 0 video pixel input for RGB 5 6 5 mode U 0 video pixel input for YUV 4 2 2 mode or V 0 ...

Page 36: ... make sure that system bus signals have perfect electrical waves System Bus signals are driven by buffers to enhance signals performance PXA255 Buffers Buffers Buffers X1 conn Data Bus Address Bus Memory Control signals Strengthed Data Bus Strengthed Address Bus Strengthed Memory Control signals The buffers signals direction control is control by CPLD on SOM A255x module 2 2 2 COM SOM A255x series...

Page 37: ... 7 2 2 5 T S SOM A255x series supports 4 wires X X Y Y resistive T S interface 2 2 6 PCMCIA CF All SOM A255x series supports 2 PCMCIA interface I F or 2 CF I F or 1 PCMCIA 1 CF I F User could check SOM A255x Series Carrier Board Design Guide to know how to design the I F PCMCIA CF I F power control circuit is designed on SOM module so PCMCIA CF I F is hot swappable Advantech strongly suggest user ...

Page 38: ...SOM A255x series CSB design guide Advantech design LCD brightness control circuit LCD contrast control circuit on SOM A255x series modules STN LCD panel needs contrast control signals In X2 LCD contrast control signals are nVCONR_INC VCONR_CS and VCONR_UnD The control signals are based on DALLAS DS1804 NV Trimmer Potentiometer to design Users could check the Advantech SOM A255x series CSB design g...

Page 39: ...tly accepts digitized RGB or YUV signals and does not accept analog signals In 16 bit mode the ZV 15 8 signals are the most significant eight video pixel inputs In 8 bit mode these signals are not used In 16 bit mode the ZV 7 0 signals are the least significant eight video pixel inputs In 8 bit mode these signals are the only eight video pixel inputs About how to wire the ZV port with NTSC PAL dec...

Page 40: ...AT VCC in X2 directly The back up power pin BAT_VCC is the only power source to supply RTC power when SOM A255x system power 3 3V 5V is off The coin battery must be 3 0V Li ion coin type The coin battery charging circuit is designed on SOM A255x so user shouldn t and needn t design the charging circuit on CSB If users don t need RTC function in CSB just let the BAT_VCC pin open 2 2 17 PCI I F Thru...

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