Advantech PCIE-1802, User Manual

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PCIE-1802 User Manual vi
Appendix A Specifications .................................... 23
A.1 General Specifications ............................................................................ 24
A.1.1 Bus Interface............................................................................... 24
A.1.2 Power Requirements .................................................................. 24
A.1.3 Physical ...................................................................................... 24
A.1.4 Environmental............................................................................. 24
A.2 Input Characteristics ............................................................................... 24
A.2.1 Maximum Operating Voltage ...................................................... 25
A.2.2 Input Overvoltage Protection ...................................................... 25
A.2.3 Input Signal Range ..................................................................... 25
A.3 AC Coupled Measurement Accuracy...................................................... 25
A.4 Flatness .................................................................................................. 26
A.5 DC Coupled Measurement Accuracy...................................................... 26
A.6 Amplifier Characteristics ......................................................................... 26
A.6.1 Input Impedance ......................................................................... 26
A.6.2 Common-Mode Rejection Ratio (CMRR) ................................... 26
A.7 Dynamic Characteristics ......................................................................... 26
A.7.1 Bandwidth ................................................................................... 26
A.7.2 AC Coupling................................................................................ 27
Figure A.1 Magnitude response of AC coupling circuit .............. 27
Figure A.2 Phase response of AC coupling circuit..................... 27
A.7.3 Idle Channel Noise ..................................................................... 28
A.7.4 Representative Measurement FFTs ........................................... 28
Figure A.3 FFT of -1 dBFS, 1 kHz Tone Acquired at 54 kS/s. ... 28
Figure A.4 FFT of -1 dBFS, 1 kHz Tone Acquired at 108 kS/s. . 29
Figure A.5 FFT of -1 dBFS, 1 kHz Tone Acquired at 216 kS/s. . 29
A.7.5 Dynamic Range (DR).................................................................. 30
A.7.6 Spurious Free Dynamic Range (SFDR) ..................................... 30
A.7.7 Signal-to-Noise Ratio (SNR)....................................................... 30
A.7.8 Total Harmonic Distortion (THD) ................................................ 31
A.7.9 Total Harmonic Distortion Plus Noise (THD+N) ......................... 31
A.7.10 Crosstalk..................................................................................... 31
A.7.11 Inter-channel Gain Mismatch...................................................... 32
A.7.12 Inter-channel Phase Mismatch ................................................... 32
A.8 Integrated Electronic Piezoelectric Excitation (IEPE) ............................. 32
A.9 Reference Clock Characteristics............................................................. 32
A.10 Triggers................................................................................................... 33
A.11 Digital I/O ................................................................................................ 33
A.12 Synchronization Input & Output .............................................................. 33
Appendix B Block Diagram ................................... 35
B.1 Function Block Diagrams ........................................................................ 36
Figure B.1 Function block diagram - overview........................... 36
Figure B.2 Function block diagram - analog input ..................... 36