Advantech PCIE-1802, User Manual

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33 PCIE-1802 User Manual
Appendix A
S
pecifications
A.10 Triggers
 Analog trigger input:
– Type: Start, delay to start, stop, or delay to stop trigger
– Source: Any analog input channel
– Level: Full scale, programmable
– Slope: Positive (rising) or negative (falling), software selectable
– Resolution: 24 bits
– Hysteresis: Programmable
 Digital trigger input:
– Type: Start, delay to start, stop, or delay to stop trigger
– Source: 2 external digital trigger inputs
– Compatibility: 3.3 V CMOS, 5 V compatible
Low: 0.8 V max.
High: 2.0 V min.
– Pull-down resistor: 50 k Ω
– Polarity: Rising or falling edge, software selectable
– Minimum pulse width: 20 ns
 Digital trigger output:
– Number of digital trigger output: 2
– Source: Analog trigger input, digital trigger input, or software trigger
– Compatibility: 3.3 V CMOS
Low: 0.6 V max.
High: 2.3 V min.
A.11 Digital I/O
 Digital Input:
– Number of digital input: 1
– Number of Interrupt: 1
– Compatibility: 3.3 V CMOS
Low: 0.6 V max.
High: 2.3 V min.
– Pull-down resistor: 50 k Ω
 Digital Output:
– Number of digital output: 2
– Compatibility: 3.3 V CMOS
Low: 0.6 V max.
High: 2.3 V min.
A.12 Synchronization Input & Output
 Synchronization Input:
– Compatibility: 3.3 V CMOS, 5 V compatible
– Pull-down resistor: 50 k Ω
 Synchronization Output:
– Compatibility: 3.3 V CMOS
Low: 0.6 V max.
High: 2.3 V min.