Advantech Co., Ltd.
31
PCI-1761 User’s Manual
www.advantech.com
C.7 Interrupt Control Register - BASE+3H/4H/5H
The
Interrupt Control Register
control the status of two interrupt signal
sources (IDI0 ~ IDI7). The user can clear the interrupt by writing its cor-
responding value to the
Interrupt Control Register
, as shown in below
table.
Table C-7: Register for interrupt control
IDI
n
CLR
Interrupt clear control bits (
n
= 0 ~ 7)
This bit must first be cleared to service the next inter
rupt.
0 Don't care
1 Clear the interrupt
IDI
n
RF
Interrupt enable control bits (
n
= 0 ~ 7)
Read this bit to Enable/Disable the interrupt.
0 Disable
1 Enable
IDI
n
EN
Interrupt triggering control bits (
n
= 0 ~ 7)
The interrupt can be triggered by a rising edge or
falling edge of the interrupt signal, as determined by
the value in this bit.
0 Rising edge trigger
1 Falling edge trigger
Write
Interrupt Control Register
Bit #
7
6
5
4
3
2
1
0
BASE +3H
IDI7EN
IDI6EN
IDI5EN
IDI4EN
IDI3EN
IDI2EN
IDI1EN
IDI0EN
BASE +4H
IDI7RF
IDI6RF
IDI5RF
IDI4RF
IDI3RF
IDI2RF
IDI1RF
IDI0RF
BASE +5H
IDI7CLR
IDI6CLR
IDI5CLR
IDI4CLR
IDI3CLR
IDI2CLR
IDI1CLR
IDI0CLR
