Appendix C Register Structure and Format
PCI-1761 User’s Manual
30
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C.6 Interrupt Status Register - BASE+3H/4H/5H
The
Interrupt Status Register
control the status of two interrupt signal
sources (IDI0 ~ IDI7).
Table C-6: Register for interrupt status
IDI
n
F
Interrupt flag bits (
n
= 0 ~ 7)
This bit is a flag indicating the status of an interrupt.
User can read this bit to get the status of the interrupt
0 No interrupt
1 Interrupt occurred
IDI
n
RF
Interrupt enable control bits (
n
= 0 ~ 7)
Read this bit to Enable/Disable the interrupt.
0 Disable
1 Enable
IDI
n
EN
Interrupt triggering control bits (
n
= 0 ~ 7)
The interrupt can be triggered by a rising edge or
falling edge of the interrupt signal, as determined by
the value in this bit.
0 Rising edge trigger
1 Falling edge trigger
Read
Interrupt Status Register
Bit #
7
6
5
4
3
2
1
0
BASE +3H
IDI7EN
IDI6EN
IDI5EN
IDI4EN
IDI3EN
IDI2EN
IDI1EN
IDI0EN
BASE +4H
IDI7RF
IDI6RF
IDI5RF
IDI4RF
IDI3RF
IDI2RF
IDI1RF
IDI0RF
BASE +5H
IDI7F
IDI6F
IDI5F
IDI4F
IDI3F
IDI2F
IDI1F
IDI0F
