Appendix C
– 39 –
PCI-1721 User’s Manual
Advantech Co., Ltd.
www.advantech.com
C.11 I/O Setting Command and Status - BASE+2AH
Table C-10 PCI-1721 Register for I/O setting
8254_CNT0
Select clock source of 82C54 counter 0
0
10 MHz clock
1
82C54 counter 0 clock (from pin 38 of CN1)
GATE0
Gate control of 82C54 counter 0
0
Disable 82C54 counter 0
1
Enable 82C54 counter 0
LDIO
Setting the LOW byte DIO as input or output
0
Output
1
Input
HDIO
Setting the HIGH byte DIO as input or output
0
Output
1
Input
FIFO_C1 ~ FIFO_C0
Select FIFO clock source
00
Clock from 82C54. The limitation is 2.5 MHz
01
5 MHz
10
10 MHz
11
Clock from external. The limitation is 10 MHz
Note:
✎
The default configuration of the digital output channels is a logic 0.
This avoids damaging external devices during system start-up or reset
since the power on status is set to the default value.
You can refer to Fig.2-3 (FIFO block diagram) to get more clear
description.
Base Addr.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2AH
W
I/O Setting Command
X
X
X
X
X
X
X
X
X
FIFO_
C1
FIFO_
C0
HDIO
LDIO
X
GATE0
8254_
CNT0
R
I/O Setting Status
0
0
0
0
0
0
0
0
0
FIFO_
C1
FIFO_
C0
HDIO
LDIO
0
GATE0
8254_
CNT0