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MIC-6311 User Manual

Chapter 1

ardware

onfiguration



KCS interface enables direct IPMI communication between the OS and BMC



BIOS failover, including a BIOS watchdog



Full BMC watchdog support, as defined in the IPMI specification



Full BMC firmware redundancy

–

Manual rollback

–

Automatic rollback in the event of update failure



HPM.1 for in field updates, supporting:

–

BMC firmware

–

FPGA

–

BIOS



UART muxing between all serial interfaces for easy console access



Additional sensors for hardware monitoring

1.3

Functional Block Diagram

Figure 1.1 MIC-6311 functional block diagram

1.4

Board Map

The figure below shows the location of the main components, jumpers, switches and
thermal sensors.

Intel

Haswell-M

4/2 Core / GT2

ECC/BGA

37W/47W

SPI

8MB

TPM

Lattice

FPGA

LCMXO2

Handle SW

RS232

User + Reset

buttons

User LEDs

HWM

Intel

Lynx Point

PCH

BMC

LPC1768

SPI / UART

UART (2x)

to RTM

8GB DDR3 onboard

FDIx2

DMI

SPI

LPC

I350AM4

P2/P3

NC-SI

3x SATAIII (6Gbps)

SPI

FRU
SDR

SEL

Power+IPMB

PCIex8

(Opt.)

(N/A)

USB 3.0 (2x)

Audio

UART (2x)

from FPGA

SATAIII, 6GB/s for 2.5

”

SSD/ SATA

PEX8733

32 Lane

PMC

64s PMC IO

2x PCIex8 (NT Capable)

PCIex4

I350 (1)

2x SerDes

2x 1GBase - T(Opt.)

USB 2.0 (2x)

DP x2

VGA

to P5

from CPU

PC
Ie

XMC

PCIe2

PCI-X

12d XMC IO

SPI

8MB

SMBus

I2C

IPMB0-A/B

to P0

Tsi721

2x PCIex4

TSI721

USB 2.

MUX

SATAII (3Gbps)

PCI-X 64b/133

SIO

UART x2

KB/MS

1600 w/ ECC

8GB DDR3 SODIMM

EEPROM

Flash

SPI

I2C

I350AM4

P0/P1

SRIO Gen2 x4
SRIO Gen2 x4

PCIex4

KB/MS

from SIO

SSD

onboard

SATAI (1.5Gbps)

Summary of Contents for MIC-6311

Page 1: ...User Manual MIC 6311 OpenVPX CPU Blade with Intel 4th Core Processor ...

Page 2: ... Advantech assumes no liability under the terms of this warranty as a consequence of such events Because of Advantech s high quality control standards and rigorous testing most of our customers never need to use our repair service If an Advantech product is defec tive it will be repaired or replaced at no charge during the warranty period For out of warranty repairs you will be billed according to...

Page 3: ...rence In such a case users are required to correct the interference at their own expense FM This equipment has passed the FM certification According to the National Fire Pro tection Association work sites are classified into different classes divisions and groups based on hazard considerations This equipment is compliant with the speci fications of Class I Division 2 Groups A B C and D indoor haza...

Page 4: ...included x 1 Daughter board for SATA HDD x 1 assembled HDD tray and screws x 1 Solder side cover x 1 assembled RJ45 to DB9 cable x 1 Warranty certificate document x 1 Safety Warnings CE FCC Class A Warning Warnings indicate conditions which if not observed can cause personal injury Caution Cautions are included to help you avoid damaging hardware or losing data e g New batteries are at risk of exp...

Page 5: ...er pour any liquid into an opening This may cause fire or electrical shock 13 Never open the equipment For safety reasons the equipment should be opened only by qualified service personnel 14 If any of the following occurs have the equipment checked by service person nel The power cord or plug is damaged Liquid has penetrated into the equipment The equipment has been exposed to moisture The equipm...

Page 6: ...t touch components on the CPU card or other cards while the PC is on Disconnect the power supply before making any configuration changes A sud den rush of power after a jumper is connected or a card installed may damage sensitive electronic components We Appreciate Your Input Please let us know whether any aspect of this product including the manual can benefit from improvements or corrections We ...

Page 7: ...tery 6 1 2 22 IPMI 6 1 2 23 BMC 6 1 3 Functional Block Diagram 7 Figure 1 1 MIC 6311 functional block diagram 7 1 4 Board Map 8 Figure 1 2 Board map 8 1 5 Jumpers and Switches 8 Table 1 3 MIC 6311 Jumper Descriptions 8 Table 1 4 MIC 6311 Switch Descriptions 8 1 5 1 Clear CMOS CN2 8 Table 1 5 CN2 Clear RTC 9 1 5 2 PMC VIO Setting JP1 9 Figure 1 3 JP11 for PMC VIO 3 3 V or 5 V 9 1 5 3 Switch Setting...

Page 8: ...ration 26 Figure 2 10Serial port configuration 27 Figure 2 11Console redirection settings 28 2 3 3 Chipset Configuration Setting 29 Figure 2 12PCH IO configuration 29 Figure 2 13System Agent SA configuration 29 Figure 2 14NB PCIe configuration 30 Figure 2 15Memory configuration 31 2 3 4 Boot Settings 31 Figure 2 16Boot settings 32 Figure 2 17Choose boot option priority 34 2 3 5 Security Settings 3...

Page 9: ...tion OEM Command 51 3 6 UART and UART Multiplexer 51 3 6 1 UART Block Diagram 51 Figure 3 2 UART functional block overview 51 3 7 ACPI 52 3 7 1 ACPI Featured Graceful Shutdown 52 3 7 2 Graceful Shutdown Timeout 52 3 8 BIOS Failover Redundancy 52 3 8 1 Overview 52 3 8 2 BIOS Boot Watchdog 52 3 9 Supported Watchdogs 52 3 9 1 Firmware Watchdog 52 3 9 2 BMC Watchdog 53 3 10 Resets 53 3 10 1 Baseboard ...

Page 10: ...1 RJ11 LAN indicator 72 A 7 1 M D PWR BMC HB and IDE Hot swap LEDs 73 Appendix B Programming the Watchdog Timer 75 B 1 Watchdog Timer Programming Procedure 76 Appendix C FPGA 77 C 1 Features 78 C 2 FPGA I O Registers 78 Table C 1 LPC I O Address Register 78 Appendix D IO Controller List 79 D 1 IO Controller List 80 Appendix E Glossary 81 E 1 Glossary 82 Appendix F BIOS Checkpoint 85 F 1 Introducti...

Page 11: ...3 Bridge Management Commands ICMB 99 Table G 14 Discovery Commands ICMB 99 Table G 15 Bridging Commands ICMB 99 Table G 16 Event Commands ICMB 100 Table G 17 OEM Commands for Bridge NetFn 100 Table G 18 Other Bridge Commands 100 G 2 PICMG IPMI Commands 101 Table G 19 AdvancedTCA PICMG 3 0 R3 0 AdvancedTCA Base Specification 101 Table G 20 HPM 1 R1 0 102 G 3 OEM Group IPMI Commands 102 Table G 21 A...

Page 12: ...MIC 6311 User Manual xii ...

Page 13: ...Chapter 1 1 Hardware Configuration This chapter describes how to configure the MIC 6311 hardware ...

Page 14: ...eliability Using Intel s latest PCH Lynx Point and advanced SATA con troller the MIC 6311 supports enhanced storage options such as a 2 5 SATA III HDD SSD socket with high storage capacity and up to 6 Gbps transfer speed The CFast socket offers an ideal alternative for implementing a cost efficient pluggable SSD and the onboard XMC PMC site with PCIe x8 2nd generation connectivity is capable of ho...

Page 15: ...0EQ is the default CPU for the MIC 6311 air cooled SKU MIC 6311 A1I8E and I5 4402E is the default CPU for the MIC 6311 conduction cooled SKU available on request Please contact your distributor or local Advantech branch for information regarding the availability of I5 4400E 4402E SKUs 1 2 4 BIOS An 8 Mbyte SPI flash featuring a board specific BIOS from AMI was designed to satisfy industrial and em...

Page 16: ...for maximum reliability Currently an 8G SATAI driver is provided with the MIC 6311 as the standard storage capacity Please contact your local Advantech branch or distributor to request the customized option 1 2 9 Serial ports One RJ 45 COM1 port RS 232 interface is provided on the front panel Two COM ports are routed to the backplane via a P5 connector and can be configured to RS232 RS485 RS422 mo...

Page 17: ...witch device as the gateway to an intelligent subsystem When configured as a sys tem controller the bridge acts as a standard transparent PCI Express to PCI PCI X Bridge The MIC 6311 receives power from the backplane and supports a rear I O The PLX PEX 8733 offers the following features PCI Interface Full compliance with the PCI Local Bus Specification Revision 3 0 PCI Power Management Spec r1 2 S...

Page 18: ...ware parameters This monitor is attached to the BMC to facilitate monitoring of the CPU temperature and core voltage 1 2 20 Super I O The MIC 6311 Super I O device supports the following legacy PC devices Serial ports COM1 and COM2 are connected to the rear I O module or front panel via a multiplexer in the FPGA The PS2 KB mouse is routed to the rear I O module 1 2 21 RTC and Battery The RTC modul...

Page 19: ...s and thermal sensors Intel Haswell M 4 2 Core GT2 ECC BGA 37W 47W SPI 8MB TPM Lattice FPGA LCMXO2 Handle SW RS232 User Reset buttons User LEDs HWM Intel Lynx Point PCH USB 2 0 3 0 BMC LPC1768 SPI UART UART 2x to RTM 8GB DDR3 onboard FDIx2 DMI SPI LPC I350AM4 P2 P3 NC SI 3x SATAIII 6Gbps SPI FRU SDR SEL Power IPMB PCIex8 P0 P1 P2 Opt P3 P4 P5 P6 N A USB 3 0 2x Audio UART 2x from FPGA SATAIII 6GB s...

Page 20: ...proximately 3 seconds 3 Set jumper CN2 as Normal 4 Turn on the system The BIOS is reset to the default setting JP1 FPGA_SW2 PCIE bridge SRIO bridge PCI bridge Thermal Sensor PCH FPGA CN2 SW3 CPU Thermal Sensor Thermal Sensor Onboard memory I350 UART_SW FPGA_SW1 Table 1 3 MIC 6311 Jumper Descriptions Number Function CN2 Clear CMOS JP1 PMC VIO Table 1 4 MIC 6311 Switch Descriptions Number Function F...

Page 21: ...C VIO 3 3 V or 5 V 1 5 3 Switch Settings Table 1 5 CN2 Clear RTC Closed Clear RTC Default Open Normal PMC1_VIO VCC3 VCC5 JP1 1 2 MINIJUMPER_2_2 0mm JP1 PH_3x1V_2 00mm 1 2 3 Note represents the key Table 1 6 FPGA_SW1 FPGA_SW2 PCIE NT Setting NT is disabled default NT is port 1 NT is port 9 FPGA_SW1 ON 2 1 FPGA_SW2 ON 2 1 3 FPGA_SW1 ON 2 1 FPGA_SW2 ON 2 1 3 FPGA_SW1 ON 2 1 FPGA_SW2 ON 2 1 3 ...

Page 22: ...backplane is set to RS422 COM2 to backplane is set to RS232 COM2 to backplane is set to RS485 COM2 to backplane is set to RS422 Table 1 7 SW3 Front COM and RTM COM1 COM2 Port Selection for BMC SIO UART Default Front COM for BMC RTM COM1 for SIO COM1 RTM COM2 for SIO COM2 Front COM for SIO COM1 RTM COM1 for BMC RTM COM2 for SIO COM2 Front COM for SIO COM2 RTM COM1 for SIO COM1 RTM COM2 for BMC UART...

Page 23: ... UART_SW An RJ 45 to DB 9 adaptor cable is provided among the MIC 6311 accessories to facilitate connectivity to external consoles or modem devices The BIOS Advanced Setup program covered in Chapter 2 provides a user interface with functions that include enabling or disabling ports and setting the port address The RS 232 standard implementation method differs between serial devices If you have pro...

Page 24: ...nd application related circuitry but does not reset the system management IPMI related circuitry A separate BMC reset button is pro vided on the front panel for resetting the BMC and related hardware 1 7 Safety Precautions Follow these simple precautions to protect yourself from harm and the products from damage To avoid electric shock always disconnect the power from your VPX chassis before direc...

Page 25: ...assembly Do not touch the components or connector pins We recommend that you assemble the device on an anti static workbench 1 8 1 HDD Installation MIC 6311 supports a 2 5 SATA hard disk drive The SATA HDD daughter board is not assembled on the MIC 6311 The SATA HDD installation steps are illustrated in the following figures Figure 1 5 Complete assembly of MIC 6311 with SATA HDD ...

Page 26: ...f the HDD then use four M2 5 screws to fas ten the bracket Figure 1 6 Fastening screws to the SATA HDD bracket 2 Place the SATA HDD with bracket on the post and insert the SATA HDD into the SATA connector Figure 1 7 Inserting the SATA HDD into the SATA connector ...

Page 27: ...h battery model number CR2032M1S8 LF Replace ment batteries can be purchased from Advantech Before ordering a battery please contact your local Advantech sales office to check availability 1750129010 BATTERY 3V 210 mAh with WIRE ASS Y CR2032M1S8 LF 1 10 Software Support Windows 7 Fedora 17 and Red Hat Enterprise Linux have been thoroughly tested on MIC 6311 Please contact your local sales represen...

Page 28: ...MIC 6311 User Manual 16 ...

Page 29: ...Chapter 2 2 AMI BIOS Setup This chapter describes how to configure the AMI BIOS ...

Page 30: ...ial screen 2 2 BIOS Setup The MIC 6311 board features an in built AMI BIOS and a SETUP utility that allows users to configure the required settings or activate specific system features When the power is turned on press the Del button during the BIOS POST Power On Self Test to access the SETUP screen Control Keys Move to select an item Enter Select Item Esc Main Menu Quit without saving changes Sub...

Page 31: ...wo main setup options are described in this section The main BIOS setup screen is shown below Figure 2 2 Main setup screen The main BIOS setup menu screen comprises two primary frames The left frame displays all options that can be configured The grayed out options cannot be con figured whereas the blue options can The right frame displays the key legend The area above the key legend is reserved f...

Page 32: ...he screen to access the sub menu for that item The details of each Advanced BIOS Setup option can be displayed by using the Arrow keys to high light the desired item All Advanced BIOS Setup options are described in this section The Advanced BIOS Setup screen is shown below The sub menus are also described in subsequent sections Figure 2 3 Advanced BIOS features setup screen 2 3 2 1 PCI Subsystem S...

Page 33: ...aximize throughput which potentially delays other devices waiting for bus ownership The latency timer does not apply to PCI Express devices VGA Palette Snoop Enables or disables VGA Palette Snoop for add on display cards VGA Palette Snooping is always disabled for on board Intel graphics PERR SERR Enable or disable to suppress the PCI bridge system error capability PCI Express Device Settings Allo...

Page 34: ...per Threading This item allows users to enable or disable Intel Hyper Threading technology Active Processor Core This item allows users to choose the number of CPU cores to activate in each processor package Limit CPUID Maximum This item allows users to limit the CPUID maximum value ...

Page 35: ...g the CPU s clock rate and is activated when the OS requests the highest processor performance state The processor performance states are defined in the Advanced Configuration and Power Interface ACPI specification an open standard supported by all major OS No additional soft ware or drivers are required to support the technology The design concept behind Turbo Boost is commonly referred to as dyn...

Page 36: ...ode is set as IDE Disabled This items indicates that SATA function is disabled SATA mode selection This item can be configured as IDE or AHCI mode SATA Controller Speed This can be Gen1 Gen2 Gen3 Disable This items allows users to disable SATA function IDE mode Set to IDE mode to use the serial ATA hard disk drives as parallel ATA physical storage devices ACHI mode Set to AHCI mode to assign SATA ...

Page 37: ...SB transfer time out value for control bulk and interrupt transfers Device Reset Time outs Sets the time out periods for USB device initialization and the Start Unit com mand to enable mass storage access operations Device Power up Delay Set the time allocated for devices to report themselves to the host controller through USB hubs When set to Auto root port devices are allocated 100 milli seconds...

Page 38: ...IC 6311 User Manual 26 2 3 2 6 Super IO Configuration Figure 2 9 Super IO configuration Serial Port Configuration For serial port IRQ and I O mode resource configuration users can select IRQ IO and MODE ...

Page 39: ...I BIOS Setup Figure 2 10 Serial port configuration 2 3 2 7 Serial Port Console Redirection Setting Console Redirection This item allows users to enable or disable console redirection or Microsoft Win dows Emergency Management Services EMS ...

Page 40: ...MIC 6311 User Manual 28 Figure 2 11 Console redirection settings Terminal Type VT UTF8 is the optimal terminal type for out of band management followed by VT100 and then VT100 ...

Page 41: ...he screen to access the sub menu for that item Users can view a Chipset Setup option by highlighting the item using the Arrow keys All Chipset Setup options are described in this section The Chipset Setup screens are shown below The sub menus are also described in subsequent sections 2 3 3 1 PCH IO Configuration Figure 2 12 PCH IO configuration 2 3 3 2 North Bridge Configuration System Agent SA Co...

Page 42: ...ws users to enable or disable VT d Enable NB CRID Enable or disable NB CRID WorkAround NB PCIe Configuration Figure 2 14 NB PCIe configuration PEG0 Gen x Select PEG0 speed Always enabled PEG This item allows users to always enable or disable PEG ...

Page 43: ...p 2 3 3 3 Memory Configuration Figure 2 15 Memory configuration DIMM Profile This item allows users to select the DIMM timing profile used Channel A B DIMM Control This item allows users enable or disable DIMMs on Channels A or B 2 3 4 Boot Settings ...

Page 44: ...on key 65535 means indefinitely Bootup NumLock State When ON the keyboard NumLock state will stay ON after booting When OFF the keyboard NumLock state will stay OFF after booting Quiet Boot If this option is set to Disabled the BIOS displays normal POST messages If enabled an OEM logo is shown instead of POST messages ...

Page 45: ...t option filter This item controls the devices that the system boots to Launch PXE OpROM Policy This item controls the execution of UEFI and Legacy PXE OpROM Option ROM Launch Storage OpROM This item controls the execution of UEFI and Legacy Storage OpROM Launch Video OpROM Policy This item controls the execution of UEFI and Legacy Video OpROM Other PCI device ROM For non network mass storage or v...

Page 46: ...ings Figure 2 18 Security settings Administrator Password Select this option and press ENTER to access the sub menu then input a password Set the Administrator password User Password Select this option and press ENTER to access the sub menu then input a password Set the User password ...

Page 47: ...et the FRB timer expiration value FRB 2 Timer Policy Allows users to configure the system response should the FRB 2 timer expire Not available if the FRB 2 timer is disabled OS Watchdog Timer If enabled this item starts a BIOS timer that can only be deactivated using Intel Management Software after the OS loads This indicates whether the OS has successfully loaded or follows the O S Boot Watchdog ...

Page 48: ...2 3 7 Save and Exit Configuration Figure 2 20 Save and exit configuration Save Changes and Exit Upon completing the system configuration select this option to save changes exit the BIOS setup menu and reboot the computer for all system configuration parameters to take effect 1 Select Exit and Save Changes in the Exit menu and press Enter The fol lowing message should appear Save Configuration Chan...

Page 49: ...s selected Defaults are designed for maximum system perfor mance but may not be ideal for all computer applications Specifically do not implement the default settings if the computer is experiencing system configura tion problems Instead select Restore Defaults in the Exit menu and press Enter Save as User Default Save all of the current settings as a user default Restore User Default Restore all ...

Page 50: ...MIC 6311 User Manual 38 ...

Page 51: ...Chapter 3 3 BMC Firmware Operation This chapter describes the BMC firmware features ...

Page 52: ...and supplied with management power the BMC discovers the slot connector Geographic Address GA The GA is used to assign a unique IPMB address according to the slot number With this IPMB address the BMC is able to communicate with other parts in the chassis The open source IPMI tool can be used to access the BMC via IPMB 3 2 2 KCS The Keyboard Controller Style KCS protocol is used as IPMI system int...

Page 53: ...MIC 6311 s Ethernet interfaces can be used for IPMI over LAN Both backplane interfaces Port 0 and 1 The front panel LAN RJ 45 connectors Following IPMItool parameters are needed to connect to the BMC vial LAN ipmitool I lan H IP Address U User P Password Command Command Line Syntax I lan Specifies Ethernet interface H IP Address IP address assigned to the BMC U User User account default administra...

Page 54: ...sor ID Sensor Type Event Reading Type Description 0 MIC 6311 IPMI FRU Device Locator 1 HOTSWAP Hot Swap Discrete Module Hot Swap sensor 12 VCC RTC VOL Voltage Threshold RTC supply voltage 15 CPU TMP Temperature Threshold CPU PECI temperature 17 INTEGRITY OEM Advantech Integrity sensor 18 BMC_WATCHDOG Watchdog 2 Discrete IPMI BMC Watchdog sensor 19 FW_PROGRESS System Firmware Progress Discrete IPMI...

Page 55: ...em firmware progress events by sending Add sel entry commands with the matching sensor type to the BMC through the KCS interface 3 3 3 4 Version Change Sensor A Version Change sensor is supported according to the IPMI specification 3 3 4 Example Sensor Data Below example shows a MIC 6311 sensor reading list printed with the open source IPMItool root localhost ipmitool sdr list TBD Table 3 3 Voltag...

Page 56: ...pecification for details on OEM sensors Event data 2 is used to identify which component the event relates to This can either be a HPM 1 component a logical component feature on the board for example FRU RTC or simply a board specific event Event data 3 7 3 identifies the action or a subcomponent For example If the com ponent in byte 2 was a HPM 1 component it might report if this was an update a ...

Page 57: ...101 b00110 b00111 b01000 b01001 b01010 b01011 b01100 b01101 b01110 b01111 b11111 Update Recovery Rollback Manual Rollback Automatic Rollback Activation Flash 0 Boot Flash 1 Boot Common Header Internal Area Chassis Info Area Board Info Area Product Info Area Multi Record Area Time synchronization Graceful Shutdown Not defined yet Not defined yet 3 2 0 Result b000 b001 b010 b011 b100 b101 b110 b111 ...

Page 58: ...ent data bytes in the SEL can be displayed with IPMItool sel get entry root localhost ipmitool sel get 0x0e SEL Record ID 000e Record Type 02 Timestamp 04 23 2012 10 13 31 Generator ID 0074 EvM Revision 04 Sensor Type OEM Sensor Number 10 Event Type Sensor specific Discrete Event Direction Assertion Event Event Data a00100 Description OEM Specific The Event Data field reflects the three needed byt...

Page 59: ...es of IPMI requests and responses under the OEM Group Net work Function explicitly identify the OEM vendor that specifies the command func tionality To be more precise the vendor IANA Enterprise Number for the defining body occupies the first three data bytes in a request and the first three data bytes fol lowing the completion code position in a response Advantech s IANA Enterprise Number used fo...

Page 60: ...ge LAN Interface selection ipmitool raw 0x2e 0x40 0x39 0x28 0x00 0x04 0x00 setting Response 39 28 00 3 5 4 LAN Controller Channel Selection And Priority In addition to the selected LAN controller interface users may need to configure each single LAN controller channel port as dedicated NC SI interface to the BMC Addi tional OEM commands for the configuration of the NC SI LAN controller channel sel...

Page 61: ...C provides OEM commands to configure these UARTs via IPMI Following COM1 COM2 port settings are available COM interfaces COM1 MUX COM2 MUX Caution Caution Verify note below about the UART dependency Table 3 8 OEM Interfaces Port Interface 0x00 COM1 0x01 COM2 Table 3 9 COM1 UART MUX Settings Setting Connection 0x00 no interface connected open 0x01 Serial over LAN SOL 0x02 Front panel Micro USB defa...

Page 62: ...e to clear the BIOS settings in NVRAM from SW side without the need of extracting the board and performing any jumper plug and re plug This command can be used to load the default BIOS set tings ipmitool raw 0x2e 0x81 0x39 0x28 0x00 Response 39 28 00 3 5 8 MAC Address Mirroring OEM Command The LAN Controller MAC addresses will also be stored in the FRU EEPROM making the MAC s available even if the...

Page 63: ...hem to their default values a single OEM command is available to perform this with only one IPMI command ipmitool raw 0x2e 0xF2 0x39 0x28 0x00 Response 39 28 00 3 6 UART and UART Multiplexer 3 6 1 UART Block Diagram Figure 3 2 UART functional block overview 3 FP LAN 2 IO 1 82580 MAC 3 4 BMC MAC Table 3 11 MAC Address Mapping Table Access MUX Real UART Virtual UART UART MUX Real UART AMC Port15 BMC...

Page 64: ... The MIC 6311 supports BIOS redundancy handled by the BMC Two BIOS SPI flashes are populated on the board This BIOS redundancy mechanism is responsi ble to manage the flash failover in case the actual selected BIOS fail to boot For example this could happen if a BIOS update over HPM 1 was done and the new BIOS version does not boot then the BMC will switch back to the previous used BIOS version 3 ...

Page 65: ... Management Controller Resets The MIC 6311 BMC support two different resets types cold and warm resets follow ing the IPMI specification 3 10 1 1 BMC Cold Reset The cold BMC reset causes default setting of all internal and external data states e g message buffers interrupt settings sensor and event configurations and FRU LED states and power up defaults to be restored Following events lead to BMC ...

Page 66: ... extension to IPMI over LAN IOL and allows to transmit serial data via LAN It s defined in the IPMI v2 0 specification and based on the RMCP protocol to encapsulate serial data in network packets and exchange them via LAN With the help of SOL user can connect to a virtual serial console e g payload x86 system from remote SOL can be used on MIC 6311 for serial based OS and pre OS communication over...

Page 67: ...figuration parameters for a given channel root localhost ipmitool lan print Set in Progress Set Complete Auth Type Support NONE MD5 PASSWORD Auth Type Enable Callback NONE MD5 PASSWORD User NONE MD5 PASSWORD Operator NONE MD5 PASSWORD Admin NONE MD5 PASSWORD OEM IP Address Source Static Address IP Address 192 168 1 1 Subnet Mask 255 255 255 0 MAC Address 00 0b ab 3e 45 87 Default Gateway IP 0 0 0 ...

Page 68: ... must be used to be able to change SOL parameters and establish SOL sessions Following general IPMItool parameters are needed for RMCP and IPMItool sol commands ipmitool I lanplus H IP Address U User P Password sol SOL Command Command Line Syntax I lanplus Specifies RMCP as desired protocol H IP Address IP address assigned to the BMC U User User account default administrator P Password Password us...

Page 69: ...tication true false privilege level user operator admin oem character accumulate level in 5 ms increments character send threshold N retry count N retry interval in 10 ms increments non volatile bit rate serial 9 6 19 2 38 4 57 6 115 2 volatile bit rate serial 9 6 19 2 38 4 57 6 115 2 3 11 2 5 SOL Session Activation Finally the IPMItool sol activate command need to be issued to establish the SOL s...

Page 70: ...MIC 6311 User Manual 58 ...

Page 71: ...Chapter 4 4 HPM 1 Update This chapter describes the update of following software firmware components Sections include BMC Firmware FPGA Configuration BIOS Image NVRAM Image BIOS Settings ...

Page 72: ...tool interface parameters which need to be used are different 4 2 BMC Firmware Upgrade 4 2 1 Load New BMC Firmware Image Type IPMItool HPM 1 upgrade command and select the new BMC firmware image root localhost ipmitool hpm upgrade mic6311_standard_hpm_fw_00_24 img PICMG HPM 1 Upgrade Agent 1 0 2 Validating firmware image integrity OK Performing preparation stage Services may be affected during upg...

Page 73: ...dure successful 4 3 2 Activate FPGA Configuration Although the new FPGA configuration is successfully stored on the board deferred version it needs to be activated before it s loaded into the FPGA chip Following two actions are needed to finish the upgrade 4 3 2 1 HPM 1 Activate Command Schedule the FPGA load with the HPM 1 Activate command root localhost ipmitool hpm activate PICMG HPM 1 Upgrade ...

Page 74: ...re users can boot the new BIOS The following two actions are needed to finish the upgrade 4 4 2 1 HPM 1 Activate Command Schedule the BIOS load with the HPM 1 Activate command root localhost ipmitool hpm activate PICMG HPM 1 Upgrade Agent 1 0 2 4 4 2 2 Payload Cold Reset A payload cold reset is required to activate the new BIOS image Component requires Payload Cold Reset The payload reset can be p...

Page 75: ... 0 24 0 22 2 6311 FPGAA 2 12 2 10 3 6311 BIOSS 0 10 0 08 4 6311 NVRAMM 0 03 Component requires Payload Cold Reset After a successful upgrade the new backup version should be the former active ver sion if Backup versions are supported And the new Active version should be the version of the used upload file ...

Page 76: ...MIC 6311 User Manual 64 ...

Page 77: ...Appendix A A Pin Assignments ...

Page 78: ...C NC GND NC NC GND Note NC No Connect Active Low Table A 2 P1 VPX I O G F E D C B A 1 GND FP1_TX0 FP1_TX0 GND FP1_RX0 FP1_RX0 2 GND FP1_TX1 FP1_TX1 GND FP1_RX1 FP1_RX1 GND 3 GND FP1_TX2 FP1_TX2 GND FP1_RX2 FP1_RX2 4 GND FP1_TX3 FP1_TX3 GND FP1_RX3 FP1_RX3 GND 5 SYS_CON GND FP2_TX0 FP2_TX0 GND FP2_RX0 FP2_RX0 6 GND FP2_TX1 FP2_TX1 GND FP2_RX1 FP2_RX1 GND 7 GND FP2_TX2 FP2_TX2 GND FP2_RX2 FP2_RX2 8 ...

Page 79: ...D GND J2 EP04 T EP04 T GND GND J2 EP04 R EP04 R 6 GND EP05 T EP05 T GND J2 GND EP05 R EP05 R GND J2 GND 7 UD GND GND J2 EP06 T EP06 T GND GND J2 EP06 R EP06 R 8 GND EP07 T EP07 T GND J2 GND EP07 R EP07 R GND J2 GND 9 x8 using 15 8 x4 using 11 8 UD GND GND J2 EP08 T EP08 T GND GND J2 EP08 R EP08 R 10 GND EP09 T EP09 T GND J2 GND EP09 R EP09 R GND J2 GND 11 UD GND GND J2 EP10 T EP10 T GND GND J2 EP1...

Page 80: ...Jn4 18 Jn4 20 n 6 GND Jn4 21 Jn4 23 GND Jn4 22 Jn4 24 GND n 7 GND Jn4 25 Jn4 27 GND Jn4 26 Jn4 28 n 8 GND Jn4 29 Jn4 31 GND Jn4 30 Jn4 32 GND n 9 GND Jn4 33 Jn4 35 GND Jn4 34 Jn4 36 n 10 GND Jn4 37 Jn4 39 GND Jn4 38 Jn4 40 GND n 11 GND Jn4 41 Jn4 43 GND Jn4 42 Jn4 44 n 12 GND Jn4 45 Jn4 47 GND Jn4 46 Jn4 48 GND n 13 GND Jn4 49 Jn4 51 GND Jn4 50 Jn4 52 n 14 GND Jn4 53 Jn4 55 GND Jn4 54 Jn4 56 GND n...

Page 81: ...D Jn6 A17 Jn6 B17 GND Jn6 D17 Jn6 E17 6 GND Jn6 A19 Jn6 B19 GND Jn6 D19 Jn6 E19 GND 7 GND USB USB GND USB USB 8 GND KB_CLK KB_DAT GND MSC_DAT A MSC_CLK GND 9 GND GND 10 GND GND GND 11 GND SERDES2 _TX SERDES2 _TX GND SERDES2 _RX SERDES2 _RX 12 GND SERDES1 _TX SERDES1 _TX GND SERDES1 _RX SERDES1 _RX GND 13 GND GBE2_DB GBE2_DB GND GBE2_DA GBE2_DA 14 GND GBE2_DD GBE2_DD GND GBE2_DC GBE2_DC GND 15 GND ...

Page 82: ...YNC GND USB3_6_T X USB3_6_ TX GND USB3_6_R X USB3_6_ RX 8 GND SATA4_TX SATA4_Tx GND SATA4_RX SATA4_RX GND 9 HDA_B CLK GND SATA5_Tx SATA5_Tx GND SATA5_RX SATA5_R X 10 GND DPC_CTRL_ DATA DPC_CTRL _CLK GND DPB_CTRL_ DATA DPB_CTRL _CLK GND 11 HDA_S DO GND SATA1_TX SATA1_TX GND SATA1_RX SATA1_R X 12 GND USB4 USB4 GND USB3 USB3 GND 13 HDA_S DI GND COM1_DC D COM1_RI GND COM1_RX COM1_T X 14 GND COM1_RTS C...

Page 83: ... PETX_N3 VPWR 5 V 4 GND GND NC JTCK GND GND NC MRSTO 5 PETX_P4 PETX_N4 3 3 V PETX_P5 PETX_N5 VPWR 5 V 6 GND GND NC JTMS GND GND 12 V 7 PETX_P6 PETX_N6 3 3 V PETX_P7 PETX_N7 VPWR 5 V 8 GND GND NC JTDI GND GND 12 V 9 NC NC NC NC NC VPWR 5 V 10 GND GND NC JTDO GND GND GA0 11 PERX_P0 PERX_N0 NC MBIST PERX_P1 PERX_N1 VPWR 5 V 12 GND GND GA1 GND GND MPRESENT 13 PERX_P2 PERX_N2 NC 3 3V_A UX PERX_P3 PERX_...

Page 84: ...GND 14 VSYNC 7 GND 15 DDC_CLK 8 GND Table A 10 CNCOM1 RJ45 Connector 1 DCD 6 DSR 2 SIN 7 RTS 3 SOUT 8 CTS 4 DTR 5 GND Table A 11 CN CN5 USB Port 1 Port 2 1 5 V fused 1 5 V fused 2 USBD0 2 USBD1 3 USBD0 3 USBD1 4 GND 4 GND Table A 12 BT1 CMOS Battery 1 BAT_VCC 2 GND Table A 13 RJ1 LAN1 Connector 1 LAN_0 5 LAN_2 2 LAN_0 6 LAN_1 3 LAN_1 7 LAN_3 4 LAN_2 8 LAN_3 ...

Page 85: ... D PWR BMC HB and IDE Hot swap LEDs Name Description PWR Green Indicates power status BMC Yellow Indicates BMC status heart beat indicates BMC is active HDD Hot Swap Yellow Blue Yellow indicates IDE activity blue indicates the board is ready to be hot swapped ...

Page 86: ...MIC 6311 User Manual 74 ...

Page 87: ...Appendix B B Programming the Watchdog Timer This appendix describes how to program the watchdog timer ...

Page 88: ... timer by rewriting the I O port 443 443 hex while simultaneously setting the address To disable the watchdog timer use the program to read I O port 444 hex The following is an example of how the watchdog timer can be programmed in BASIC 10 REM Watchdog timer example program 20 OUT H443 data REM Start and restart the watchdog 30 GOSUB 1000 REM Your application task 1 40 OUT H443 data REM Reset the...

Page 89: ...Appendix C C FPGA This appendix describes the FPGA configuration ...

Page 90: ... ICH9R LPC signals The Debug Port Unit is used to decode POST codes The Hot Swap Out Of Service LED Control Unit is used to con trol the blue LED during Hot Insert and Hot Remove operations The Drone Mode Unit is used to disable the VPX The other signals in the Miscellaneous Unit are for interfacing with corresponding I O interface signals Table C 1 LPC I O Address Register LPC Address I O Type De...

Page 91: ...Appendix D D IO Controller List ...

Page 92: ...TA Intel Lynx Point SATA to backplane Intel Lynx Point CFast Intel Lynx Point USB 2 0 3 0 to front panel Intel Lynx Point USB 2 0 3 0 to back plane Intel Lynx Point Audio to backplane Intel Lynx Point Front panel RJ45 Intel I350AM4 SERDES to backplane Intel I350AM4 GBE to backplane Intel I350AM4 UART to front panel Lattice LCMXO2 UART to backplane Lattice LCMXO2 ...

Page 93: ...Appendix E E Glossary ...

Page 94: ...gement Bus IPMI Intelligent Platform Management Interface KCS Keyboard Controller Style LED Light Emitting Diode LPC Low Pin Count MAC Medium Access Control NCSI Network Controller Sideband Interface NVRAM Non Volatile Random Access Memory OS Operating System PCB Printed Wiring Board PCI Peripheral Component Interconnect PCIe Peripheral Component Interconnect Express PHY Physical layer Interface P...

Page 95: ... MIC 6311 User Manual Appendix E Glossary SPI Serial Peripheral Interface SPD Serial Presence Detect SW Software ULV Ultra Low Voltage UART Universal Asynchronous Receiver Transmitter XTM Extension Module ...

Page 96: ...MIC 6311 User Manual 84 ...

Page 97: ...Appendix F F BIOS Checkpoint ...

Page 98: ...irmware model specified in the Intel Platform Innovation Framework for EFI the Frame work The Framework refers to the following boot phases which may apply to var ious status code and checkpoint descriptions Security SEC initial low level initialization Pre EFI Initialization PEI memory initialization Driver Execution Environment DXE main hardware initialization Boot Device Selection BDS system se...

Page 99: ... started 0x11 Pre memory CPU initialization started 0x12 Pre memory CPU initialization CPU module specific 0x13 Pre memory CPU initialization CPU module specific 0x14 Pre memory CPU initialization CPU module specific 0x15 Pre memory North Bridge initialization started 0x16 Pre memory North Bridge initialization North Bridge module specific 0x17 Pre memory North Bridge initialization North Bridge m...

Page 100: ...Bridge initialization South Bridge module specific 0x3E Post memory South Bridge initialization South Bridge module specific 0x3F 0x4E OEM post memory initialization codes 0x4F DXE IPL started PEI Error Codes 0x50 Memory initialization error Invalid memory type or incompatible memory speed 0x51 Memory initialization error SPD reading failed 0x52 Memory initialization error Invalid memory size or m...

Page 101: ...initialization CPU module specific 0x68 PCI host bridge initialization 0x69 North Bridge DXE initialization started 0x6A North Bridge DXE SMM initialization started 0x6B North Bridge DXE initialization North Bridge module specific 0x6C North Bridge DXE initialization North Bridge module specific 0x6D North Bridge DXE initialization North Bridge module specific 0x6E North Bridge DXE initialization ...

Page 102: ... future AMI codes 0xA0 IDE initialization started 0xA1 IDE reset 0xA2 IDE detect 0xA3 IDE enable 0xA4 SCSI initialization started 0xA5 SCSI reset 0xA6 SCSI detect 0xA7 SCSI enable 0xA8 Setup verification password 0xA9 Start of setup 0xAA Reserved for ASL see the ASL Status Codes section below 0xAB Setup input wait 0xAC Reserved for ASL see the ASL Status Codes section below 0xAD Ready to boot even...

Page 103: ...tus Code Description 0x01 System entering S1 sleep state 0x02 System entering S2 sleep state 0x03 System entering S3 sleep state 0x04 System entering S4 sleep state 0x05 System entering S5 sleep state 0x10 System waking from the S1 sleep state 0x20 System waking from the S2 sleep state 0x30 System waking from the S3 sleep state 0x40 System waking from the S4 sleep state 0xAC System transitioned in...

Page 104: ...MIC 6311 User Manual 92 ...

Page 105: ...Appendix G G IPMI PICMG Command Subset Supported by BMC ...

Page 106: ...hdog Timer 27 6 App 24h Mandatory Yes Get Watchdog Timer 27 7 App 25h Mandatory Yes Table G 3 BMC Device and Messaging Commands Command IPMI v2 0 Ref NetFn CMD IPMI BMC Req Advantech BMC support Set BMC Global Enables 22 1 App 2Eh Mandatory Yes Get BMC Global Enables 22 2 App 2Fh Mandatory Yes Clear Message Flags 22 3 App 30h Mandatory Yes Get Message Flags 22 4 App 31h Mandatory Yes Enable Messag...

Page 107: ...No Get Channel Payload Ver sion 24 9 App 4Fh No Get Channel OEM Payload Info 24 10 App 50h No Master Write Read 22 11 App 52h Mandatory Yes Get Channel Cipher Suites 22 15 App 54h Yes Suspend Resume Payload Encryption 24 3 App 55h No Set Channel Security Keys 22 25 App 56h Yes Get System Interface Capa bilities 22 9 App 57h No Table G 4 Chassis Device Commands Command IPMI v2 0 Ref NetFn CMD IPMI ...

Page 108: ...ast Processed Event ID 30 5 S E 14h Mandatory No Get Last Processed Event ID 30 6 S E 15h Mandatory No Alert Immediate 30 7 S E 16h Optional No PET Acknowledge 30 8 S E 17h Optional No Table G 7 Sensor Device Commands Command IPMI v2 0 Ref NetFn CMD IPMI BMC Req Advantech BMC support Get Device SDR Info 35 2 S E 20h Optional Yes Get Device SDR 35 3 S E 21h Optional Yes Reserve Device SDR Repos ito...

Page 109: ...y No Partial Add SDR 33 14 Storage 25h Mandatory No Delete SDR 33 15 Storage 26h Optional No Clear SDR Repository 33 16 Storage 27h Mandatory Yes Get SDR Repository Time 33 17 Storage 28h Optional Man datory Yes Set SDR Repository Time 33 18 Storage 29h Optional Man datory Yes Enter SDR Repository Update Mode 33 19 Storage 2Ah Optional No Exit SDR Repository Update Mode 33 20 Storage 2Bh Mandatory...

Page 110: ...rial Modem Configura tion 25 1 Transport 10h Optional Man datory No Get Serial Modem Configura tion 25 2 Transport 11h Optional Man datory No Set Serial Modem Mux 25 3 Transport 12h Optional No Get TAP Response Codes 25 4 Transport 13h Optional No Set PPP UDP Proxy Trans mit Data 25 5 Transport 14h Optional No Get PPP UDP Proxy Trans mit Data 25 6 Transport 15h Optional No Send PPP UDP Proxy Packe...

Page 111: ...y No Get Bridge Proxy Address ICMB Bridge 09h Optional Man datory No Get ICMB Connector Info ICMB Bridge 0Ah Optional Man datory No Get ICMB Connection ID ICMB Bridge 0Bh Optional Man datory No Send ICMB Connection ID ICMB Bridge 0Ch Optional Man datory No Table G 14 Discovery Commands ICMB Command IPMI v2 0 Ref NetFn CMD IPMI BMC Req Advantech BMC support Prepare For Discovery ICMB Bridge 10h Opt...

Page 112: ... Send ICMB Event Message ICMB Bridge 33h Optional Man datory No Get Event Destination ICMB Bridge 34h Optional Man datory No Get Event Reception State ICMB Bridge 35h Optional Man datory No Table G 17 OEM Commands for Bridge NetFn Command IPMI v2 0 Ref NetFn CMD IPMI BMC Req Advantech BMC support OEM Commands ICMB Bridge C0h FEh Optional Man datory No Table G 18 Other Bridge Commands Command IPMI ...

Page 113: ...t Device Locator Record ID 3 39 PICMG 0Dh Yes Set Port State 3 59 PICMG 0Eh No Get Port State 3 60 PICMG 0Fh No Compute Power Properties 3 82 PICMG 10h No Set Power Level 3 84 PICMG 11h No Get Power Level 3 83 PICMG 12h No Renegotiate Power 3 91 PICMG 13h No Get Fan Speed Properties 3 86 PICMG 14h No Set Fan Level 3 88 PICMG 15h No Get Fan Level 3 87 PICMG 16h No Bused Resource 3 62 PICMG 17h No G...

Page 114: ...d 3 10 PICMG 33h Yes Get upgrade status 3 2 PICMG 34h Yes Activate firmware 3 11 PICMG 35h Yes Query Self test Results 3 12 PICMG 36h Yes Query Rollback status 3 13 PICMG 37h Yes Initiate Manual Rollback 3 14 PICMG 38h Yes Table G 19 AdvancedTCA PICMG 3 0 R3 0 AdvancedTCA Base Specification Table G 21 Advantech OEM Commands Command NetFn CMD IPMI BMC Req Advantech BMC support Store Configuration S...

Page 115: ...Appendix H H Driver Tools ...

Page 116: ...ion of different access methods and IPMITool calls The IPMITool source code can be downloaded from the official project page http ipmitool sourceforge net The Open IPMI Linux device driver is designed as a full function IPMI device driver with the following features Allows multiple users Allows multiple interfaces Allows both kernel and userland things to use the interface Fully supports the watch...

Page 117: ...105 MIC 6311 User Manual Appendix H Driver Tools ...

Page 118: ...ations are subject to change without notice No part of this publication may be reproduced in any form or by any means electronic photocopying recording or otherwise without prior written permis sion of the publisher All brand and product names are trademarks or registered trademarks of their respective companies Advantech Co Ltd 2014 ...

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