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1.7 General Layout Guidelines
This section provides general layout guideline for high speed signals, PCI Express,
USB and Display port.
1.7.1 Impedance
In a high-speed signaling environment, signal trace impedances must be controlled in
order to maintain good signal quality across the motherboard. Signal trace
impedance is a function of the following three factors:
• Motherboard stack up
• Dielectric constant of the PCB substrate
• Signal trace width and thickness
1.7.2 Crosstalk
The following list of recommendations should be followed to help reduce the
crosstalk on the motherboard:
•
Do not allow high-speed signals to cross plane splits.
•
Reference critical signals to ground planes.
•
Do not cut ground planes unless it is absolutely necessary.
•
Reduce the length of signals that are routed parallel.
•
Provide analog signals with guard shields or guard rings.
•
Keep analog signals away from digital signals.
1.7.3 Reference Planes
The high-frequency return path for any signal lies directly beneath the signal on the
adjacent layer. Providing a solid plane underneath a signal greatly reduces problems
with signal integrity, timing, and EMI because the plane provides a direct return path
for that signal. There are two cases where a signal can change its reference plane:
crossing a plane split or changing signal layers. If either of these are unavoidable,
techniques must be used to minimize the negative impact caused by changing
reference planes.
1.7.4 Crossing Plane Splits
When crossing a plane split, a 0.1-μF or 0.01-μF stitching capacitor with a 0402 or
smaller body size should be used. Place the stitching capacitors as close as possible
to the traces crossing the split, as shown in Figure 1.7-1.
