Advantech IDK2121WNK2FHA2EES, User Manual

Page: 23 / 39

17 IDK-2121W User Manual
Chapter 3
S
ignal Characteristics
Note1: Input signals of odd and even clock shall be the same timing.
Note2: Please follow VESA.
15 RxE1- Negative LVDS differential data input (Even data)
16 RxE1+ Positive LVDS differential data input (Even data)
17 VSS Power Ground
18 RxE2- Negative LVDS differential data input (Even data)
19 RxE2+ Positive LVDS differential data input (Even data)
20 RxEC- Negative LVDS differential clock input (Even clock)
21 RxEC+ Positive LVDS differential clock input (Even clock)
22 RxE3- Negative LVDS differential data input (Even data)
23 RxE3+ Positive LVDS differential data input (Even data)
24 VSS Power Ground
25 NC No connection (for AUO test only. Do not connect)
26 NC No connection (for AUO test only. Do not connect)
27 NC No connection (for AUO test only. Do not connect)
28 VDD Power +5V
29 VDD Power +5V
30 VDD Power +5V
Table 3.1: Pin Description