Advantech EVA-X4300, User Manual

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EVA-X4300 System Design Guide 14
18. Ensure that any signal passing between those sections runs ONLY through the
“bridge”, and run the signals on a layer adjacent to the bridge to maintain RF
return path.
19. If analog or digital power is not required in the isolated area, the unused power
plane can be redefined as a second ground plane, referenced to the main
ground plane by stitches of vias within the isolated area.
20. Connect system Power-on and H/W Reset to “Power-good” input of EVA-
X4300, then use “/PCI_RST” output of EVA-X4300 to reset ALL peripherals.
21. The power-on-strap pins are combined with the memory address bus, which
belong to DRAM power category. So the pull-high resistors should connect to
the same supply (VCCO) of DRAM interface. That is:
For detail of power-on-straps function, please refer to the EVA-X4300 data sheet.
22. Do follow the power-on sequence to prevent excessive current from the power
supplies during power-up and power-down periods:
! Power-up core supply (VDD_CORE), and then power-up the I/O supply
(DVDD).
!
Power-down I/O supply (DVDD), and then power-down the core supply
(VDD_CORE).
23. Recommend Termination:
24. Recommended PCB stack up:
a. 4 layers
DRAM type Supply (V) Note
SDR 3.3
DDR2 1.8
Signal Zs ( Ω ) Termination( Ω ) Trace impedance ( Ω )
Clocks 24M 26 22 60
PCI clock 7.2 22 60
PCI signal 13.2 51 60
DDR Clocks 19 33 90, Differential
DDR signal 19 33 60
Layer Type Description Material/ Thickness
1 Signal Top Routing Copper/ 0.5~1oz
FR4/ 5mil
2 Plane Ground Copper/ 1oz
FR4/ 40mil
3 Plane Power Copper/ 1oz
FR4/ 5mil
4 Signal Bottom Routing Copper/ 0.5~1oz