Advantech ARK-7480, User Manual

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23 Chapter 3
(*): means default setting of the jumper/function
3.7 CMOS Clearance (JP3)
The CMOS RAM is powered by an onboard button cell battery. When you
finish BIOS setup, the data in CMOS RAM will be automatically backed up
to Flash ROM. Applicant can force system to clear the data in COMS RAM
by setting the JP3.
(*): means default setting of the jumper/function
3.8 Installation of the Central Processing Unit (CPU)
The panel PC's central processing unit (CPU) can be upgraded to improve
system performance. The ARK-7480 Embedded Box Computer provides
COM1 5V 1-3 closed
12V 3-5 closed
Wake On Ring* Open
COM2 5V 2-4 closed
12V 4-6 closed
Wake On Ring* Open
COM3 5V 7-9 closed
12V 9-11 closed
Wake On Ring* Open
COM4 5V 8-10 closed
12V 10-12 closed
Wake On Ring* Open
COM5 5V 13-15 closed
12V 15-17 closed
Wake On Ring* Open
COM6 5V 14-16 closed
12V 16-18 closed
Wake On Ring* Open
Table 3.5:
JP3 : Clear CMOS Jumper (JP3)
Function
Pin Setting
Normal * 1-2 closed*
CLEAR RTC 2-3 closed