ADLINK Technology Inc.
LEC-iMX8M User’s Guide
Page 22
copyright © 2021 ADLINK Technology Inc.
4.3.1.1
LVDS0/LVDS1 mode
Name
Pin # Description
I/O Type
I/O
Level
Power
Domain
PU / PD
Comments
LVDS0_0-
LVDS0_1 -
LVDS0_2-
LVDS0_3-
S125
S126
S128
S129
S131
S132
S137
S138
Primary LVDS channel differential pair
data lines
O LVDS
LCD
Runtime
L
LVDS0_CK-
S134
S135
Primary LVDS channel differential pair
clock lines
O LVDS
LCD
Runtime
LCD0_VDD_EN
S133 Primary LVDS channel power enable,
active high
O
CMOS
1.8V
Runtime
LCD0_BKLT_EN
S127 Primary LVDS channel backlight enable,
active high
O
CMOS
1.8V
Runtime
LCD0_BKLT_PWM
S141 Primary LVDS channel brightness control
through pulse width modulation (PWM)
O
CMOS
1.8V
Runtime
LVDS1_0-
LVDS1_1 -
LVDS1_2-
LVDS1_3-
S111
S112
S114
S115
S117
S118
S120
S121
Secondary LVDS channel differential pair
data lines
O LVDS
LCD
Runtime
L
LVDS1_CK-
S108
S109
Secondary LVDS channel differential pair
clock lines.
O LVDS
LCD
Runtime
LCD1_VDD_EN
S116 Secondary panel power enable, active
high
O
CMOS
1.8V
Runtime
LCD1_BKLT_EN
S107 Secondary panel backlight enable, active
high
O
CMOS
1.8V
Runtime
LCD1_BKLT_PWM
S122 Secondary panel brightness control
through pulse width modulation (PWM)
O
CMOS
1.8V
Runtime
