LEC-EL Product specification
SGET SMARC Rev 2.1
Page 3
copyright © 2021 ADLINK Technology Inc.
4.3.1.1
LVDS0/LVDS1 mode
Name
Pin #
Description
I/O
Type
I/O
Level
Power
Domain
PU / PD
Comments
LVDS0_0-
LVDS0_1 -
LVDS0_2-
LVDS0_3-
S125
S126
S128
S129
S131
S132
S137
S138
Primary LVDS Channel Differential
Pair Data Lines
O LVDS
Runtime
100 ohm differential termination across the differential
pairs at the endpoint of the signal path, usually on the
display assembly.
L
LVDS0_CK-
S134
S135
Primary LVDS Channel Differential
Pair Clock Lines
O LVDS
Runtime
100 ohm differential termination across the differential
pair at the endpoint of the signal path, usually on the
display assembly.
LCD0_VDD_EN
S133
Primary LVDS Channel Power Enable
O
CMOS
1.8V
Runtime
Active high
LCD0_BKLT_EN
S127
Primary LVDS Channel Backlight Enable
O
CMOS
1.8V
Runtime
Active high
LCD0_BKLT_PWM
S141
Primary LVDS Channel Brightness Control
O
CMOS
1.8V
Runtime
Through pulse width modulation (PWM)
LVDS1_0-
LVDS1_1 -
LVDS1_2-
LVDS1_3-
S111
S112
S114
S115
S117
S118
S120
S121
Secondary LVDS Channel Differential Pair Data
Lines
O LVDS
Runtime
100 ohm differential termination across the differential
pairs at the endpoint of the signal path, usually on the
display assembly.
L
LVDS1_CK-
S108
S109
Secondary LVDS Channel Differential Pair
Clock Lines
O LVDS
Runtime
100 ohm differential termination across the differential
pair at the endpoint of the signal path, usually on the
display assembly.
Summary of Contents for SMARC MODULE LEC-EL
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