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Operations

PCIe-9529

Operations

This chapter contains information regarding analog input, trigger-
ing and timing for the PCIe-9529.

3.1 Functional Block Diagram

3.2 Analog Input Channel

3.2.1

Analog Input Front-End Configuration

Figure 3-1: Analog Input Architecture

CLK

Synthesizer

Reference &

Calibration

10 MHz

2-bit /12.288MHz

TRG IN

Board to Board Conn x2

ADC Ctrl

CH0

Quad

24bit ADC

ADC

CH1

CH2

CH3

CH4

CH5

CH6

CH7

PGA

2-bit / 12.288MHz

ADC Ctrl

Control

DC-DC\

LDO

JFET

Buffer

OPAMP

3.3V

12V

FPGA

ADC Control

Trigger Control

Data Processing

FIFO Interface

PCIe Controller

PCIe Gen1

PCIe Gen1 x4

Slot

ADC
BUS

SSI Bus [0..7]

SSI_TIMEBASE

3.3V

12V

Quad

24bit ADC

BUF

PGA

BUF

PGA

SSI

Connector

Digital

BUS

24-bit ADC

JFET OPAMP

330nF / 25V

CAL+

CAL-

IEPE-

1MR

330nF / 25V

SPST

IEPE+

49.9R

SPST

CARR

DATA

ADC Ctrl

SCK

Vref

10k

Cal+

PGA

Signal Switch

X10

Summary of Contents for PCIe-9529

Page 1: ...Advance Technologies Automate the World PCIe 9529 8 CH 24 Bit 192 kS s Dynamic Signal Acquisition Module User s Manual Manual Rev 2 00 Revision Date July 11 2014 Part Number 50 11255 1000...

Page 2: ...ii Revision History Revision Release Date Description of Change s 2 00 July 11 2014 Initial Release...

Page 3: ...tion even if advised of the possibility of such damages Environmental Responsibility ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance wi...

Page 4: ...CAUTION Information to prevent minor physical injury component dam age data loss and or program corruption when trying to com plete a task WARNING Information to prevent serious physical injury compo...

Page 5: ...neral Specifications 9 1 4 Schematics and I O 11 1 5 Software Support 13 1 5 1 SDK 13 1 5 2 DSA DASK 13 2 Getting Started 15 2 1 Package Contents 15 2 2 Installation Environment 15 2 3 Installing the...

Page 6: ...5 1 Timebase 27 3 5 2 DDS Timing vs ADC 27 3 5 3 Filter Delay in ADC 27 3 6 Synchronizing Multiple Modules 28 3 6 1 SSI_TIMEBASE 29 3 6 2 SSI_SYNC_START 29 3 6 3 SSI_AD_TRIG 30 A Appendix Calibration...

Page 7: ...c Range 192kS s 8 Figure 1 6 PCIe 9529 Side View 11 Figure 1 7 PCIe 9529 I O Array 12 Figure 3 1 Analog Input Architecture 17 Figure 3 2 Linked List of PCI Address DMA Descriptors 21 Figure 3 3 Trigge...

Page 8: ...viii List of Figures This page intentionally left blank...

Page 9: ...t 9 Table 3 1 Input Range and Data Format 19 Table 3 2 Input Range Midscale Values 19 Table 3 3 ADC Sample Rates vs DDS Output Clock 20 Table 3 4 Preferred Characteristics for Analog Triggers 24 Table...

Page 10: ...x List of Tables This page intentionally left blank...

Page 11: ...PE signal conditioning for accelerometers and microphones The PCIe 9529 is auto calibrated with an onboard reference cir cuit calibrating offset and acquiring analog input errors Following auto calibr...

Page 12: ...kS s to 192 kS s 768 S s increments for Fs 108 kS s 576 S s increments for 54 kS s Fs 108 kS s 192 S s increments for 8KS s Fs 54kS s Over voltage protection Differential 42 4V Pseudo differential pos...

Page 13: ...s 74 6 1 Shorted input Input Range V CMRR1 dB 1V 65 10V 80 1 Input frequency 1 kHz Sample rate1 3 dB bandwidth Fs 108 kS s 0 4863 FS Fs 108 kS s 0 22 FS 1 Disable digital filter when Fs 108 kS s Enab...

Page 14: ...litude 2 Measurement Includes harmonics Dynamic Range dBFS 1 Input Range V Fs 54 kS s Fs 108 kS s Fs 192 kS s 1V 10V 107 100 100 1 1 kHz input tone and 60 dBFS input amplitude SNR dBc 1 Input Range V...

Page 15: ...to 42 kHz 1V 96 94 95 10V 96 92 95 1 1 kHz input tone and 1 dBFS input amplitude IMD dBc 1 2 Input Range V Fs 54 kS s Fs 108 kS s Fs 192 kS s 1V 103 99 99 10V 105 101 101 1 CCIF 14 kHz 15 kHz 2 6 dBF...

Page 16: ...ch Figure 1 1 Analog Input Channel Bandwidth 1dBFS 108kS s Input Range V Phase Mismatch 1 1V 10V 1 khz 20 khz 86 4 khz 0 1 0 442 1 64 1 1 dBFS input amplitude 10 2 10 3 10 4 10 5 25 20 15 10 5 0 Magni...

Page 17: ...1 3 Spurious Free Dynamic Range 54kS s 10 1 10 0 10 1 4 5 4 3 5 3 2 5 2 1 5 1 0 5 0 Frequency Hz Magnitude dB Response when AC coupling enabled 0 0 5 1 1 5 2 2 5 x 10 4 160 140 120 100 80 60 40 20 0...

Page 18: ...S s 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 x 10 4 160 140 120 100 80 60 40 20 0 Frequency Hz Magnitude dB SFDR 108 kS s 1V Input Range 1 dBFS and 1 kHz Sine Wave Input 0 1 2 3 4 5 6 7 8 9 x 10 4 160 140 120...

Page 19: ...rigger Source Mode Trigger source Software external digital trigger analog trigger and SSI Trigger mode Post trigger and delay trigger Digital Trigger Input Sources Front panel SMB connector Compatibi...

Page 20: ...non condensing Storage Temperature 20 C 80 C Relative humidity 10 90 non condensing Calibration Onboard reference 5 000 V Temperature coefficient 5 0 ppm C Warm up time 15 minutes Power Consumption P...

Page 21: ...Introduction 11 PCIe 9529 1 4 Schematics and I O Figure 1 6 PCIe 9529 Side View NOTE NOTE All dimensions are in mm 100 36 59 05 176 42...

Page 22: ...12 Introduction The PCIe 9529 I O array is labeled to indicate connectivity as shown Figure 1 7 PCIe 9529 I O Array...

Page 23: ...eir own programs ADLINK pro vides the following software development kits Z DAQPilot for LabVIEW Z Toolbox adapter for MATLAB 1 5 2 DSA DASK DSA DASK includes device drivers and DLL for Windows XP 7 8...

Page 24: ...14 Introduction This page intentionally left blank...

Page 25: ...nstall equipment in well lit areas on flat sturdy surfaces with access to basic tools such as flat and cross head screwdrivers preferably with magnetic heads as screws and standoffs are small and easi...

Page 26: ...il its card edge connector is resting on the slot receptacle 5 Install the bracket retaining screw to secure the PCI express digitizer to the back panel rail 6 Replace the computer cover CAUTION The e...

Page 27: ...DC ADC ADC ADC ADC ADC ADC ADC ADC CH1 CH2 CH3 CH4 CH5 CH6 CH7 PGA PGA 2 bit 12 288MHz ADC Ctrl IO Control DC DC LDO JFET Buffer OPAMP 3 3V 5V 12V FPGA ADC Control Trigger Control Data Processing FIFO...

Page 28: ...oupling are available With DC coupling DC offset present in the input signal is passed to ADC and is indicated if the signal source has a small level of offset voltage or if DC content of the signal i...

Page 29: ...29 is 2 s complement Table 3 1 Input Range and Data Format Table 3 2 Input Range Midscale Values 3 2 3 ADC and Analog Input Filter ADC Analog to Digital Converter The PCIe 9529 provides sigma delta an...

Page 30: ...transfer a PCI bus mastering DMA is essen tial for continuous data streaming as it helps to achieve the full potential PCI Express bus bandwidth The bus mastering control ler releases the burden on th...

Page 31: ...data transfer size except the physical storage capacity of the system Users can also link descriptor nodes circularly to achieve a multibuffered DMA A linked list comprising three DMA descriptors Each...

Page 32: ...d function calls to begin the operation External Digital Trigger An external digital trigger is generated when a TTL rising edge or a falling edge is detected at the SMB connector on the front panel A...

Page 33: ...er signals to SSI Bus Number 5 Analog Trigger The PCIe 9529 analog trigger circuitry can be configured to monitor one analog input channel from which data is acquired Selection of an analog input chan...

Page 34: ...H3 CH4 CH5 CH6 and CH7 during use of an external analog trigger source The trigger level can be set by software with 24 bit resolution with characteristics as shown Table 3 4 Preferred Characteristics...

Page 35: ...Two trigger modes applied to trigger sources initiate different data acquisition timings when a trigger event occurs as applied to analog input and output functions Post Trigger Mode If post trigger...

Page 36: ...n of data after several trigger events as shown When the number of triggers is defined the PCIe 9529 acquires specific sample data each time a trigger is accepted All sampled data is stored in onboard...

Page 37: ...Table 3 5 Timing Relationship between ADC and PLL Clock 3 5 3 Filter Delay in ADC Filter delay indicates time required for data propagation through a converter Both AI channels experience filter delay...

Page 38: ...nization Interface SSI Dedicate routing of timebase clock and trigger signals onto the SSI Bus enables the PCIe 9529 to simplify synchronization between multiple modules The bidirectional SSI I O prov...

Page 39: ...As output the SSI_TIMEBASE signal transmits the onboard ADC timebase through the SSI bus As input the PCIe 9529 accepts the SSI_TIMEBASE signal as the source of the timebase 3 6 2 SSI_SYNC_START Befo...

Page 40: ...6 3 SSI_AD_TRIG As output the SSI_AD_TRIG signal reflects the trigger event sig nal in an acquisition sequence As input the PCIe 9529 accepts the SSI_AD_TRIG signal as the trigger event source The sig...

Page 41: ...on the calibration constants are recorded to Bank 1 When PCIe 9529 boots the driver accesses the calibration con stants and is automatically set to hardware In the absence of user assignment the drive...

Page 42: ...libration it is recommended to warm up the PCIe 9529 for at least 20 minutes and remove connected cables NOTE NOTE It is not necessary to manually factor delay into applications as the PCIe 9529 drive...

Page 43: ...urn off power and unplug any power cords cables X To avoid electrical shock and or damage to equipment Z Keep equipment away from water or liquid sources Z Keep equipment away from high heat or high h...

Page 44: ...viced by authorized technicians when Z The power cord or plug is damaged Z Liquid has penetrated the equipment Z It has been exposed to high humidity moisture Z It is not functioning or does not funct...

Page 45: ...300 Fang Chun Rd Zhangjiang Hi Tech Park Pudong New Area Shanghai 201203 China Tel 86 21 5132 8988 Fax 86 21 5132 3588 Email market adlinktech com ADLINK Technology Beijing Address 1 E 801 100085 Rm 8...

Page 46: ...o Dong Seocho Gu Seoul 137 070 Korea Tel 82 2 2057 0565 Fax 82 2 2057 0563 Email korea adlinktech com ADLINK Technology Singapore Pte Ltd Address 84 Genting Lane 07 02A Cityneon Design Centre Singapor...

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