ADLINK Technology MI-110, User Manual

Page: 54 / 88

42 BIOS Setup
4.4 Advanced Chipset Features
DRAM Clock/Drive Control
When set to “BySPD”, the DRAM timing parameters are set
according to DRAM SPD (Serial Presence Detect). When dis-
abled, one can manually set the DRAM timing parameters using
the sub items below. Set to “BySPD” if not sure.
CAS Latency Time
Controls the latency between the SDRAM Read command and the
time data actually becomes available.
DRAM RAS# to CAS# Delay
Controls the latency between the DDR SDRAM active command
and the read/write command.
DRAM RAS# Precharge
Controls the idle clocks after issuing a precharge command to the
DDR SDRAM.
Precharge delay (tRAS)
This setting controls the precharge delay, which determines the
timing delay for DRAM precharge.
System Memory Frequency
Allow to choose different frequency of memory module.