ADLINK Technology LEC-iMX6, Technical Reference

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Interfaces 13
LEC-iMX6
3.3 HDMI (High-Definition Multimedia Interface)
The HDMI port utilizes the following HDMI pins on the SMARC interface:

1 Clock pair (P101/P102)

3 Data pairs (P92/P93; P95/P96; P98/P99)

Service signals (P104-P107)
The HDMI interface is compliant with HDMI 1.4, HDMI CTS 1.4a, DVI 1.0 (with DVI-to-HDMI
adapter), and HDCP 1.4. The module supports Monitor Detection for plug and unplug detection.
The voltage level of the HDMI interface is 1.8V.
3.4 Camera PCAM
The Parallel Camera interface supports 10-Bit video with up to 240 MHz clock speed.
The voltage level of the PCAM interface is 1.8V.
3.5 Camera MIPI-CSI
The LEC-iMX6 brings out signals for an MIPI CSI-2 serial camera interface. This serial camera
port supports up to 1000 Mbps/lane in 1/2-lane mode.
The voltage level of the MIPI CSI-2 interface complies with the MIPI CSI specification.
3.6 PCIe
The module supports a PCIe port x1 lane, Gen 2.0 from the CPU, providing up to 5 Gb/s band-
width in each direction. An optional PCIe switch IC allows for three lanes of PCIe expansion and
an optional SPI Flash. The i.MX 6 PCIe includes 3 Cores: Dual Mode core, Root Complex core,
and Endpoint core.
The LEC-iMX6 PCIe configurations include the following options:

1x PCIe 1x Gen 2.0

3x PCIe 1x Gen 2.0 using the optional PCIe switch

Service signals per lane:

One PCIe wake-up input signal:
3.7 Gigabit Ethernet
The LEC-iMX6 uses an Ethernet PHY, which is connected to the CPU Ethernet controller with
an RGMII interface. The PHY circuitry provides a standard IEEE 802.3 Ethernet interface for
1000BASE-T, 100BASE-TX, and 10BASE-Te applications. The following bullets highlight the
Ethernet interface:

Operates on TCP/IP, UDP/IP, and ICMP/IP protocol data or on IP header only

Supports IPv4 and IPv6
NOTE: The Ethernet throughput is limited to 400 Mbit/s by the Freescale SoC.
PCIE_X_CKREQ# PCIE_X_RST# PCIE_X_PRSNT#
PCIE_WAKE# Input