ADLINK Technology cPCIS-3100 Series, User Manual

Page: 31 / 41

Backplane Options
•
21
u
P4 pin assignments of system slot are all reserved for rear I/O
u
P5 pin assignments of system slot are all reserved for rear I/O or
connect to the secondary IDE connector according to the following
definition.
Pin Z A B C D E F
22 GND N/C N/C N/C N/C N/C GND
21 GND N/C N/C
SDD8 SDD7 SPWRGD
GND
20 GND N/C N/C
SDD9
N/C
SDD6
GND
19 GND N/C N/C
SDD11 SDD10 SDD5
GND
18 GND N/C N/C
SDD12
N/C
SDD4
GND
17 GND N/C N/C N/C N/C N/C GND
16 GND N/C N/C N/C N/C
SDD3
GND
15 GND N/C N/C N/C N/C N/C GND
14 GND N/C N/C
SDD13
N/C
SDD2
GND
13 GND N/C N/C N/C
SDD14 SDD1
GND
12 GND N/C N/C
SDD15
N/C
SDD0
GND
11 GND N/C N/C N/C
DDRQ1 DIOW1#
GND
10 GND N/C N/C
DIOR1# PDIAG SIORDY
GND
9 GND N/C N/C N/C N/C
DDACK1#
GND
8 GND N/C N/C
SDA1
N/C
SIRQ
GND
7 GND N/C N/C N/C
SDA2 SDA0
GND
6 GND N/C N/C
SCS3#
N/C
SCS1#
GND
5 GND N/C N/C N/C N/C N/C GND
4 GND N/C N/C N/C N/C N/C GND
3 GND N/C N/C N/C N/C N/C GND
2 GND N/C N/C N/C N/C N/C GND
1 GND N/C N/C N/C N/C N/C GND
Note: 1. The N/C pins are no connection to any other pins.
2. The signal pins are reserved for matching with cPCI-6200A CPU
boards. These signals are connected to the secondary IDE
connector. All these signals are reserved for users’ own rear I/O
application, if users do not use the secondary IDE port.
4.1.4 I/O Slot Pin assignments
u
P1 pin assignments are compliant to PCIMG 2.0 R3.0, 32-bit
CompactPCI standard
Note: 1. The HEATHY# signals is bypassed to Ground by a 0.01uF
capacitor.
2. The REQ64# and ACK64# signals are with 2.7KO pull high.
3. The graphical address (GA) of the peripheral slot is assigned by
the backplane. They are identical with their respective physical slot
number.
u
P2, P3, P5 pin assignments are all none-connected and reserved for
rear I/O application.
u
P4 pin assignments are compliant to PICMG 2.5 H.110 standard