ADLINK Technology CoreModule 920 Reference Manual Download

Page: 19 / 64

Chapter 2

Product Overview

CoreModule 920

Reference Manual

Figure 2-3. Component Locations (Top Side)

Figure 2-4. Component Locations (Bottom Side)

CM920_T

op_Comp_a

Key:
U1

- CPU

- DDR3 SDRAM

U10

- DDR3 SDRAM

U11

- DDR3 SDRAM (ECC)

U12

- PCH

U14

- Gigabit Ethernet PHY Transceiver

U15

- Gigabit Ethernet MAC & PHY Controller

U16

- Gigabit Ethernet EEPROM

U17

- PCIe to PCI Bridge

U48

- HDMI Level Shifter

U11

U10

U16

U17

U12

U48

U15

U14

CM920_Bottom_Comp_b

Key:
T1

- Gigabit Ethernet 1 Transformer

- Gigabit Ethernet 2 Transformer

- DDR3 SDRAM

U18

- LPC to UART Controller

U20

- RS-232 Transceiver - COM1

U21

- RS-232 Transceiver - COM2

U22

- SSD (Solid State Drive)

U27

- Hardware Monitor

U28

- BIOS

U66

- EEPROM, DDR3 SPD

U67

- EEPROM, PCIe to PCI Bridge

- PCIe/104

(See Header and Connector table)

SW1

- PCI Express x16 Configuration Switch

(See Header and Connector table)

U22

U28

SW1

U27

U66

U21

U20

U67

U18

1 2

Summary of Contents for CoreModule 920

Page 1: ...CoreModule 920 Single Board Computer Reference Manual P N 50 1Z144 1010 ...

Page 2: ...software designers and applications engineers ADLINK Technology Inc assumes you are qualified to design and implement prototype computer equipment ii Reference Manual CoreModule 920 TRADEMARKS CoreModule and the Ampro logo are registered trademarks and ADLINK Little Board LittleBoard MightyBoard MightySystem MilSystem MiniModule ReadyBoard ReadyBox ReadyPanel ReadySystem and RuffSystem are tradema...

Page 3: ...nmental Specifications 20 Thermal Cooling Requirements 20 Chapter 3 Hardware 21 Overview 21 CPU 22 Graphics 22 Memory 22 Interrupt Channel Assignments 23 Memory Map 23 I O Address Map 24 Serial Interfaces 25 USB Interface 27 Ethernet Interfaces 28 Video Interfaces 29 Power Interface 31 User GPIO Interface 32 Utility Interface 33 Power Button 33 Reset Switch 33 Speaker 33 System Fan 33 Battery 34 E...

Page 4: ...2 8 Mechanical Overview Top Side 18 Figure 2 9 i7 3517UE Peak In Rush Current and Duration 19 Figure 2 10 Stack Heights of Cooling Assemblies 20 Figure 3 1 Oops Jumper Serial Port DB9 35 Figure 3 2 Serial Console Jumper 35 Figure 4 1 Main BIOS Setup Screen 39 Figure 4 2 Advanced BIOS Setup Screen 40 Figure 4 3 Chipset BIOS Setup Screen 46 Figure 4 4 Boot BIOS Setup Screen 49 Figure 4 5 Security BI...

Page 5: ...n Signals J23 30 Table 3 12 Power Interface Pin Signals J24 31 Table 3 13 User GPIO1 Interface Pin Signal Descriptions J26 32 Table 3 14 User GPIO2 Interface Pin Signal Descriptions J27 32 Table 3 15 Utility Interface Pin Signals J21 33 Table 3 16 System Fan Pin Signals J22 33 Table 3 17 External Battery Input Header J12 34 Table 3 18 GLAN1 External LED Pin Signals J2 34 Table 3 19 GLAN2 External ...

Page 6: ...Contents vi Reference Manual CoreModule 920 ...

Page 7: ...rd busses and signals Pin signal definitions for industry standard interfaces References The following list of references may help you successfully complete your custom design Industry Standard Specifications PCI 104 Express Specification Revision 2 0 February 2011 Web site http www pc104 org pci104_Express_specs php PCI 104 Specification Web site http www pc104 org pci_104_specs php PCI Express S...

Page 8: ...ontrollers ethernet controllers html Atmel Corporation and the AT25128B SSHL B Ethernet EEPROM Data sheet http www atmel com dyn resources prod_documents doc8535 pdf Fintek Inc and the F81216AU I LPC to 4 UART Controller Data sheet http www fintek com tw files productfiles F81216_V032P pdf Texas Instruments and the XIO2001IPNP PCIe to PCI bridge Web site http www ti com sitesearch docs universalse...

Page 9: ... Manual CoreModule 920 Reference Manual 3 NOTE If you are unable to locate the datasheets using the links provided search the internet using the name of the manufacturer or component model and locate the documents you need ...

Page 10: ...Chapter 1 About This Manual 4 Reference Manual CoreModule 920 ...

Page 11: ...elf stacking expansion modules to provide additional capabilities such as Additional serial and parallel ports Analog or high speed digital I O Data Acquisition Analog In Out USB 2 0 expansion modules IEEE 1394 FireWire expansion modules Standard VGA video output PCI 104 Express compliant expansion modules can be stacked with a CoreModule SBC avoiding the need for large expensive card cages and ba...

Page 12: ...d voltage levels and a Utility interface for Power button Reset switch and Speaker output The PCH connects to two 10 pin Gigabit Ethernet interfaces through two PCIe x1 lanes The CoreModule 920 can be expanded through the PCIe expansion bus using the PCI 104 and PCIe 104 interfaces for additional system functions These interfaces offer compact self stacking modular expandability The PCI 104 interf...

Page 13: ...a rate interface Supports 32 bit data bus Supports DDR3 1333MHz memory Expansion Buses PCI bus version 2 3 at 33MHz PCIe bus version 2 0 at 100MHz SATA Interface Supports two SATA 3 0 ports from the BD82QM67 PCH Supports up to 6Gb second data transfer rate Supports independent DMA operation Supports Native Command Queuing Provides Auto Activate for DMA Supports Hot Plug features Provides two stand...

Page 14: ...ol Supports full duplex or half duplex mode Full duplex mode supports transmit and receive frames simultaneously Supports IEEE 802 3x Flow control in full duplex mode Half duplex mode supports enhanced proprietary collision reduction mode Video Interfaces VGA HDMI LVDS and PEG Provide VGA outputs Resolutions up to 2048x1536 pixels at 75Hz Integrated 340 4MHz RAMDAC with 32 bit color RGB output pro...

Page 15: ... eight GPIO ports Supports sample code in BSP QuickDrive Utility Interface Power Button Reset Switch Speaker Miscellaneous Real Time Clock RTC with external replaceable battery Battery free boot Oops Jumper support Serial Console support Watchdog Timer Logo Screen Splash SSD Solid State Drive Hardware Monitor voltage and temperature ...

Page 16: ...nector SATA1 Connector SSD PCIe to PCI Bridge PCIe 104 Connector GPIO GPIO Header GPIO GPIO Header LPC Serial Header RS232 Transceiver RS232 Transceiver Serial Header LPC to UART Controller F81216 SMBus USB 2 0 Ports 4 5 USB 2 0 Ports 0 1 USB 2 0 Ports 2 3 VBAT CPLD Battery Header Utility Header Intel 82579LM PHY Transceiver GLAN1 LED Header GLAN2 LED Header GLAN1 Header Transformer Transformer PC...

Page 17: ...es high speed data transfer PCH Platform Controller Hub U12 Intel BD82QM67 PCH I O Hub for common user interfaces Provides Southbridge interfaces and off loads some Northbridge functions from the CPU Gigabit Ethernet PHY Transceiver U14 Intel 82579LM Single port Gigabit Ethernet PHY Transceiver for GLAN1 interface Provides a standard IEEE 802 3 Ethernet interface for Ethernet transfer rates up to ...

Page 18: ...ce Flash Memory chip for firmware Stores BIOS in Flash Memory HDMI Level Shifter U48 ST Microelectr onics STHDLS101TQTR HDMI level shift IC for HDMI video Converts HDMI differential input from the PCH to TMDS differential output for the HDMI interface EEPROM DDR3 U66 on bottom side see Figure 2 4 Atmel AT24C02C Two Wire Serial EEPROM for SPD Serial Presence Detect Provides storage for System Memor...

Page 19: ...e U48 HDMI Level Shifter U1 U3 U5 U11 U8 U10 U16 U17 U12 U48 U15 U14 CM920_Bottom_Comp_b Key T1 Gigabit Ethernet 1 Transformer T2 Gigabit Ethernet 2 Transformer U4 DDR3 SDRAM U6 DDR3 SDRAM U7 DDR3 SDRAM U9 DDR3 SDRAM U18 LPC to UART Controller U20 RS 232 Transceiver COM1 U21 RS 232 Transceiver COM2 U22 SSD Solid State Drive U27 Hardware Monitor U28 BIOS U66 EEPROM DDR3 SPD U67 EEPROM PCIe to PCI B...

Page 20: ... USB 2 0 PCIe x1 and PCI interfaces SAMTEC ASP 129646 03 J7 PCI 104 Top Bottom 120 pin 0 079 2mm standard PCI 104 connector for PCI interfaces EPT 264 60303 12 J8 HDMI Micro Top 19 pin 0 016 0 04mm standard micro connector for HDMI video port MOLEX 46765 0001 J10 SATA0 Top 7 pin 0 050 1 27mm standard connector for SATA 3 0 port 0 WIN WIN WATM 07DBN4B2B8UW J12 Battery Top 2 pin 0 049 1 25mm shroude...

Page 21: ...om 4 pin dip switch for selecting CPU PCIe x16 lane configurations WIN WIN DHN 02 T V T R Switch Positions Lane Configurations 1 OFF 2 OFF 1x16 Default 1 OFF 2 ON 2x8 1 ON 2 OFF Reserved 1 ON 2 ON 1x8 2x4 NOTE The pinout tables in Chapter 3 of this manual identify pin sequence using the following method A 10 pin header with two rows of pins using odd even numbering where pin 2 is directly across f...

Page 22: ...A 2DSA Enable 3 3V 1 2 Default Enable 5V 2 3 JP2 PCI 104 Voltage Selection HIROSE A4B 3PA 2DSA Enable 3 3V 1 2 Default Enable 5V 2 3 CM920_Top_Conn_b Key H11 GLAN1 H15 USB 0 1 H16 COM2 J2 LED GLAN1 PHY Transceiver J3 LED GLAN2 Gb Controller J5 PCIe 104 J6 PCIe 104 see Bottom Component View J7 PCI 104 J8 HDMI Micro J10 SATA0 J12 Battery J13 SATA1 J14 GLAN2 J17 VGA J18 COM1 J21 Utility J22 Fan J23 L...

Page 23: ... upper board surface This does not include the cooling solution which is required on all versions of the board and may increase the height of the board Component height should not exceed 0 345 8 763mm from the upper surface of the board and 0 190 4 826mm from the lower surface of the board See Figure 2 10 on page 20 for the stack heights of the cooling solutions on the board Weight 0 12 kg 0 25 lb...

Page 24: ...E All dimensions are given in inches Black square pins on headers and connectors represent pin 1 Black square pins on right angle headers represent pin 2 CM920_Top_dmn_a 0 20 5 08mm 0 33 8 38mm 1 60 49 53mm 2 00 49 53mm 3 45 87 63mm 3 58 90 93mm 3 78 96 01mm 0 00 0 00 0 20 5 08mm 3 35 85 09mm 3 55 90 17mm 4 05 102 87mm 0 50 12 70mm ...

Page 25: ...hard drive with Windows XP one USB mouse and one USB keyboard BIT Burn In Test operating configuration includes Idle configuration as well as two USB thumb drives two serial COM ports with loop backs a second SATA hard drive as slave and two Ethernet ports Figure 2 9 i7 3517UE Peak In Rush Current and Duration Table 2 5 Power Supply Requirements Parameter 1 7GHz CPU 3517UE Input Type Regulated DC ...

Page 26: ...eration in the Extended temperature range if the CPU speed is locked at 800MHz To lock the CPU speed at 800MHz use the Power Consumption setting field in the CPU PPM Configuration submenu of the Advanced BIOS Setup Screen on page 40 See Figure 2 10 for height measurements of the cooling assemblies Figure 2 10 Stack Heights of Cooling Assemblies Table 2 6 Environmental Requirements Parameter Condit...

Page 27: ...I O Address Map Serial Port Interfaces USB Interfaces Ethernet Interface Video Interfaces VGA LVDS HDMI PEG Power Interface GPIO Interface Utility Interface Power Button Reset Switch Speaker System Fan Interface Battery Interface Ethernet LED Interface Miscellaneous SSD Solid State Drive Time of Day RTC Oops Jumper BIOS Recovery Serial Console Hot Cable Hardware Temperature and Voltage Monitor Wat...

Page 28: ...phics features of the CPU include support for DirectX 11 0 OpenGL 3 1 DirectX Video Acceleration DXAV Advanced Scheduler 2 0 1 0 and XPDM Memory The CoreModule 920 employs one 1333MHz memory channel with one rank of eight system memory chips and one additional chip for ECC The board provides up to 2GB of extended memory using 2Gb DDR3 SDRAM chips The CPU features Intel FMA Fast Memory Access techn...

Page 29: ...X PCI INTA Automatically Assigned PCI INTB Automatically Assigned PCI INTC Automatically Assigned PCI INTD Automatically Assigned USB Automatically Assigned Video Automatically Assigned Ethernet Automatically Assigned NOTE The IRQs for USB Video and Ethernet are automatically assigned by the BIOS Plug and Play logic Local IRQs assigned during initialization can not be used by external devices Tabl...

Page 30: ...stem reserved 0081 0083 DMA Page Registers 0084 0086 System reserved 0087 DMA Page Register 0088 System reserved 0089 008B DMA Page Registers 008C 008E System reserved 008F DMA Page Register 0090 0091 System reserved 0092 Fast A20 gate and CPU reset 0093 009F System reserved 00A0 00A1 Slave Interrupt Controller 00A2 00BF System reserved 00C0 00DF Slave DMA Controller 2 00E0 00EF System reserved 00...

Page 31: ...t environments this input is driven by DTR as part of the DTR DSR handshake 2 S1_DSR 6 COM1 Data Set Ready Indicates external serial device is powered initialized and ready Used as hardware handshake with DTR for overall readiness 3 S1_RXD 2 COM1 Receive Data Serial port receive data input is typically held at a logic 1 mark when no data is being transmitted and is held Off for a brief interval af...

Page 32: ...eld at a logic 1 mark when no data is being transmitted and is held Off for a brief interval after an On to Off transition on the RTS line to allow the transmission to complete 4 S2_RTS 7 COM2 Request To Send Indicates serial port is ready to transmit data Used as hardware handshake with CTS for low level flow control 5 S2_TXD 3 COM2 Transmit Data Serial port transmit data output is typically held...

Page 33: ... Table 3 6 USB0 and USB1 Interface Pin Signals H15 Pin Signal Description 1 USB PWR_0 USB0 Power VCC 5V 5 power goes to the port through an on board fuse Port is disabled if this input is low 2 USB PWR_1 USB1 Power VCC 5V 5 power goes to the port through an on board fuse Port is disabled if this input is low 3 CONN_USB0_N USB0 Port Data Negative 4 CONN_USB1_N USB1 Port Data Negative 5 CONN_USB0_P ...

Page 34: ...uplex mode the Ethernet controller adheres to the IEEE 802 3x Flow Control specification In half duplex mode performance is enhanced by a proprietary collision reduction mechanism IEEE 802 3 compatible physical layer to wire transformer IEEE 802 3u Auto Negotiation support Fast back to back transmission support with minimum interframe spacing IFS IEEE 802 3x auto negotiation support for speed and ...

Page 35: ... and Table 3 11 for the LVDS pin signal definitions The HDMI interface is a standard HDMI micro connector and those pin signals are not defined in this manual The PEG signals are part of the standard PCIe 104 interface and are not defined in this manual VGA Supports resolutions up to 2048x1536 pixels at 75Hz Provides integrated 340 4MHz RAMDAC with 32 bit color Provides RGB output by three 8 bit D...

Page 36: ...lay 2 HSYNC Horizontal Sync This signal is used for the digital horizontal sync polarity is programmable or sync interval 2 5V output to the VGA display 3 DDC CLK Display Control Clock 4 RED Red This is the Red analog output signal to the VGA display 5 DDC DATA Display Control Data 6 GREEN Green This is the Green analog output signal to the VGA display 7 VDD5V0 Power This is the 5 volts 5 power si...

Page 37: ...nd 13 LVDSA_DAT0_P LVDS A DATA Positive Line 0 14 LVDSA_DAT0_N LVDS A DATA Negative Line 0 15 LBKLT_CTL Panel Backlight Control 16 LVDD_EN Enable Panel Power 17 LDDC_CLK Display Data Channel Clock 18 LDDC_DATA Display Data Channel Data 19 LBKLT_EN Enable Backlight Inverter 20 NC Not Connected Table 3 12 Power Interface Pin Signals J24 Pin Signal Descriptions 1 GND Ground 2 5V 5 Volts 3 GND Ground ...

Page 38: ...of the GPIO1 interface which provides a 6 pin single row header with 0 079 2mm pitch Note The shaded areas denote ground All GPIO pins are in the Core Power Well of the PCH Table 3 14 describes the pin signals of the GPIO2 interface which provides a 6 pin single row header with 0 079 2mm pitch Note The shaded table cells denote ground All GPIO pins are in the Core Power Well of the PCH Table 3 13 ...

Page 39: ... allows the user to re boot the system Speaker The speaker signal provides sufficient signal strength to drive an external 1W 8 Beep speaker at an audible level through pins 4 and 5 on the Utility header The speaker signal is driven from an on board amplifier and the CPU Table 3 15 describes the pin signals of the Utility interface which provides a 5 pin single row header with 0 100 2 54mm pitch N...

Page 40: ... Table 3 19 defines the signals for the GLAN2 LED header that indicates Ethernet links and activity using a single row of 4 pins with 0 049 1 25mm pitch Note The shaded table cell denotes power Configure Ethernet LEDs for Active Low operation Table 3 17 External Battery Input Header J12 Pin Signal Description 1 V_BATT 3 0 volts DC 2 GND Ground Table 3 18 GLAN1 External LED Pin Signals J2 Pin Signa...

Page 41: ...ebooting the system To convert a standard DB9 connector to an Oops jumper short together the DTR 4 and RI 9 pins on the front of the connector as shown in Figure 3 1 on the Serial Port 1 DB9 connector Figure 3 1 Oops Jumper Serial Port DB9 Serial Console The CoreModule 920 BIOS supports the serial console or console redirection feature This I O function is ANSI compatible with a serial terminal or...

Page 42: ...et Enable the WDT using Watchdog Timer of the Boot menu in BIOS Setup Set the WDT for a time out interval in seconds between 1 and 255 in one second increments in the Boot Configuration screen Ensure you allow enough time for the boot process to complete and for the OS to boot The OS or application must tickle the WDT as soon as it comes up This can be done by accessing the hardware directly or th...

Page 43: ...e BIOS setup through a remote serial terminal or PC 1 Turn on the power supply to the CoreModule 920 and enter the BIOS Setup Utility using a local video display 2 Ensure the BIOS feature Serial Port Console Redirection is set to Enabled under the Advanced menu 3 Accept the default options or make your own selections for the balance of the Console Redirection fields and record your settings 4 Ensu...

Page 44: ... can be a company logo or any custom image the user wants to display during the boot process The custom image can be displayed as the first image on screen during the boot process and remain there while the OS boots depending on the options selected in BIOS Setup Logo Image Requirements Please contact your ADLINK Sales Representative for more information on OEM Logo Utility requirements NOTE The s...

Page 45: ...ime Advanced ACPI CPU SATA GPIO USB Hardware Monitor Serial Ports Serial Port Console Chipset PCH I O System Agent Boot Boot up Settings Boot Options Boot Order Security Setting or changing Passwords Save Exit Exiting with or without changing settings loading and restoring Optimal or User Defaults Aptio Setup Utility Copyright C 20XX Amreican Megatrends Inc BIOS Information BIOS Vendor American Me...

Page 46: ...U Configuration Intel R Core TM i7 3517UE 1 70GHz CPU Signature XXXxX Microcode Patch XX Max CPU Speed XXXX MHz Aptio Setup Utility Copyright C 20XX American Megatrends Inc Version X XX XXXX Copyright C 20XX American Megatrends Inc CM920_BIOS_Advanced_a Main Advanced Chipset Boot Security Save Exit CPU Configuration ACPI Settings GPIO Configuration PCH FW Configuration Intel R Anti Theft Technolog...

Page 47: ...imum Disabled Enabled Execute Disable Bit Disabled Enabled Intel Virtualization Technology Disabled Enabled SATA Configuration SATA Controller s Enabled Disabled SATA Mode Selection IDE AHCI RAID Serial ATA Port 0 Empty Software Preserve Unknown Serial ATA Port 1 Empty Software Preserve Unknown Serial ATA Port 2 GLS85LS1008P C X XGB Software Preserve Supported GPIO Configuration GPIO0 Mode Input O...

Page 48: ...ts USB transfer time out 1 sec 5 sec 10 sec 20 sec Device reset time out 10 sec 20 sec 30 sec 40 sec Device power up delay Auto Manual ADT 7490 H W Monitor ADT 7490 Pc Health Status Module temperature XX C ADT7490 temperature XX C CPU temperature By PECI XX C Vtt X XXX V Vccp X XXX V Vcc X XXX V 5V X XXX V 12V XX XXX V F81216 Super IO Configuration Super IO Chip Fintek F81216 F81216 Serial Port 1 ...

Page 49: ...I Bits per second 9600 19200 38400 57600 115200 Data Bits 7 8 Parity None Even Odd Mark Space Stop Bits 1 2 Flow Control None Hardware RTS CTS VT UTF8 Combo Key Support Disabled Enabled Recorder Mode Disabled Enabled Resolution 100x31 Disabled Enabled Legacy OS Redirection 80x24 80x25 Putty KeyPad VT100 LINUX XTERMR6 SCO ESCN VT400 COM2 Console Redirection Disabled Enabled Console Redirection Sett...

Page 50: ...Legacy OS Redirection 80x24 80x25 Putty KeyPad VT100 LINUX XTERMR6 SCO ESCN VT400 Intel ICC Integrated Clock Control options Use Watchdog timer for ICC Disabled Enabled Turn off unused PCI PCIe clocks Disabled Enabled Lock ICC registers Static only All registers Clock Manipulation ICC Overclocking Lib X X X XX DIV 1S DIV 1S GFX Maximum supported frequency XXX XX MHz Minimum supported frequency XXX...

Page 51: ... MHz Current SSC mode Down Current SSC X XX DIV4 DIV4 GFX Bending Maximum supported frequency XXX XX MHz Minimum supported frequency XXX XX MHz Current frequency XXX XX MHz Current SSC mode Down Current SSC X XX DIV 1NS DIV 1NS GFX Maximum supported frequency XXX XX MHz Minimum supported frequency XXX XX MHz Current frequency XXX XX MHz Current SSC mode Down Current SSC X XX DIV 2NS DIV 2NS Not us...

Page 52: ... Setup Screen Figure 4 3 Chipset BIOS Setup Screen PCH IO Configuration Intel PCH RC Version X X X X Intel PCH SKU Name QM67 Intel PCH Rev ID XX XX Aptio Setup Utility Copyright C 20XX American Megatrends Inc Version X XX XXXX Copyright C 20XX American Megatrends Inc CM920_BIOS_Chipset_a Main Advanced Chipset Boot Security Save Exit PCH IO Configuration System Agent SA Configuration Setting Descri...

Page 53: ...ion System Agent Bridge Name IvyBridge System Agent RC Version X X X X VT d Capability Supported VT d Disabled Enabled Graphics Configuration IGFX VBIOS Version XXXX IGfx Frequency XXX MHz Primary Display Auto IGFX PEG Internal Graphics Disabled Enabled GTT Size 1MB 2MB Aperture Size 128MB 256MB 512MB DVMT Pre Allocated 32MB 64M 96M 128M 160M 192M 224M 256M 288M 320M 352M 384M 416M 448M 480M 512M ...

Page 54: ...LVDS Backlight Inverter PWM Inverted PWM Normal NB PCIe Configuration PEG0 XXXX PEG0 Gen X Auto Gen1 Gen2 Gen3 PEG0 ASPM Disabled Auto ASPM L0s ASPM L1 ASPM L0sL1 Enable PEG Disabled Enabled Auto Memory Configuration Memory RC Version X X X X Memory Frequency XXXX MHz Total Memory XXXX MB DDR3 DIMM 0 XXXX MB DDR3 DIMM 1 Not Present DIMM 2 Not Present DIMM 3 Not Present CAS Latency tCL X Minimum de...

Page 55: ...ion 1 P1 GLS85LS1032A CS 32GBN A101C0 Disabled Aptio Setup Utility Copyright C 20XX Amreican Megatrends Inc Boot Configuration Boot Option Priorities Driver Option Priorities CSM16 Module Version XX XX Version X XX XXXX Copyright C 20XX American Megatrends Inc CM920_BIOS_Boot_a Main Advanced Chipset Boot Security Save Exit Quiet Boot Disabled Fast Boot Disabled Bootup NumLock State On Option ROM M...

Page 56: ...tility Copyright C 20XX American Megatrends Inc Password Description If ONLY the Administrator s password is set then this only limits access to Setup and is only asked for when entering Setup If ONLY the User s password is set then this is a power on password and must be entered to boot or enter Setup In Setup the User will have Administrator rights The password length must be in the following ra...

Page 57: ...d Set User Password Save Exit BIOS Setup Screen Figure 4 6 Save Exit BIOS Setup Screen Aptio Setup Utility Copyright C 20XX American Megatrends Inc Version X XX XXXX Copyright C 20XX American Megatrends Inc CM720_BIOS_Save Exit_a Main Advanced Chipset Boot Security Save Exit Save Changes and Exit Save Changes and Reset Discard Changes and Exit Discard Changes and Reset Save Options Boot Override S...

Page 58: ... and reset Yes No Discard Changes and Reset Reset without saving Yes No Save Options Save Changes Save configuration Yes No Discard Changes Load Previous Values Yes No Restore Defaults Load Optimized Defaults Yes No Save as User Defaults Save configuration Yes No Restore User Defaults Restore User Defaults Yes No Boot Override SATA PS GLS85LS1008P CS XXGB Save configuration and reset Yes No Launch...

Page 59: ...and then going to the Ask a Question feature Requests can be submitted 24 hours a day 7 days a week You will receive immediate confirmation that your request has been entered Once you have submitted your request you must log in to go to My Stuff area where you can check status update your request and access other features Download Service This service is also free and available 24 hours a day at h...

Page 60: ...ss 15 rue Emile Baudot 91300 Massy CEDEX France Tel 33 0 1 60 12 35 66 Fax 33 0 1 60 12 35 66 Email france adlinktech com ADLINK Technology Japan Corporation Address ͱ101 0045 ᵅҀ䛑गҷ ऎ 䤯 ފ 3 7 4 374 ɛɳ 4F KANDA374 Bldg 4F 3 7 4 Kanda Kajicho Chiyoda ku Tokyo 101 0045 Japan Tel 81 3 4455 3722 Fax 81 3 5209 6013 Email japan adlinktech com ADLINK Technology Inc Korean Liaison Office Address 昢殾柢昢爎割昢爎...

Page 61: ...ule 920 Reference Manual 55 Table A 1 Technical Support Contact Information Continued ADLINK Technology Inc Israeli Liaison Office Address 6 Hasadna St Kfar Saba 44424 Israel Tel 972 9 7446541 Fax 972 9 7446542 Email israel adlinktech com ...

Page 62: ...Appendix A Technical Support 56 Reference Manual CoreModule 920 ...

Page 63: ...LED interface description 34 features 8 interface description 28 specification reference 1 expansion buses features 7 specification references 1 F fan interface description 33 features list 7 G GPIO interface description 32 interface features 9 graphics description 22 H hardware monitor description 36 feature 9 specification reference 2 HDMI features 29 interface features 8 level shifter specifica...

Page 64: ...ure 9 specification reference 2 supported features battery 9 34 console redirection 35 Core i7 CPU 7 22 DDR3 SDRAM 7 Ethernet 8 28 external speaker 33 I O address map 24 IRQ assignments 23 jumper headers 16 LED external Ethernet 34 LVDS interface 30 memory map 23 Oops jumper BIOS recovery 9 35 optional system fan header 33 reset switch 33 serial console 9 35 serial ports 7 25 Splash Screen OEM Log...

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