Express-BD7
System Resources
37
6. System
Resources
6.1. System Memory Map
Memory Range
Target
Dependency/Comments
0000 0000h-000D FFFFh
0010 0000h-TOM
(Top of Memory)
Main Memory
TOM registers in Host controller
000E 0000h-000E FFFFh
LPC or SPI
Bit6 in BIOS Decode Enable register is set
0000F 0000h-0000F FFFFh
LPC or SPI
Bit7 in BIOS Decode Enable register is set
FEC_ _000h-FEC_ _040h
IO(x) APIC inside
intel(R) Xeon(R)
Processor D-1500
Producy Family
_ _is controlled using APIC Range Select(ASEL) field
and APIC Enable (AEN) bit
FEC1 0000h-FEC1 7FFFh
PCI Express Port 1
PCI Express Root Port 1 I/OxAPIC Enable(PAE) set
FEC1 8000h-FEC1 FFFFh
PCI Express Port 2
PCI Express Root Port 2 I/OxAPIC Enable(PAE) set
FEC2 0000h-FEC2 7FFFh
PCI Express Port 3
PCI Express Root Port 3 I/OxAPIC Enable(PAE) set
FEC2 8000h-FEC2 FFFFh
PCI Express Port 4
PCI Express Root Port 4 I/OxAPIC Enable(PAE) set
FEC3 0000h-FEC3 7FFFh
PCI Express Port 5
PCI Express Root Port 5 I/OxAPIC Enable(PAE) set
FEC3 8000h-FEC3 FFFFh
PCI Express Port 6
PCI Express Root Port 6 I/OxAPIC Enable(PAE) set
FEC4 0000h-FEC4 7FFFh
PCI Express Port 7
PCI Express Root Port 7 I/OxAPIC Enable(PAE) set
FEC4 8000h-FEC4 FFFFh
PCI Express Port 8
PCI Express Root Port 8 I/OxAPIC Enable(PAE) set
FEC0 0000h-FFC7 FFFFh
FF80 0000h-FF87 FFFFh
LPC or SPI(or PCI)
Bit 8 in BIOS Decode Enable register is set
FEC8 0000h-FFCF FFFFh
FF88 0000h-FF8F FFFFh
LPC or SPI(or PCI)
Bit 9 in BIOS Decode Enable register is set
FED0 0000h-FFD7 FFFFh
FF90 0000h-FF97 FFFFh
LPC or SPI(or PCI)
Bit 10 in BIOS Decode Enable register is set
FFD8 0000h-FFDF FFFFh
FF98 0000h-FF9F FFFFh
LPC or SPI(or PCI)
Bit11 in BIOS Decode Enable register is set
FFE0 0000h-FFE7 FFFFh
FFA0 0000h-FFA7 FFFFh
LPC or SPI(or PCI)
Bit 12 in BIOS Decode Enable register is set
FFE8 0000h-FFEF FFFFh
FFA8 0000h-FFAF FFFFh
LPC or SPI(or PCI)
Bit 13 in BIOS Decode Enable register is set
FFF0 0000h-FFF7 FFFFh
FFB0 0000h-FFB7 FFFFh
LPC or SPI(or PCI)
Bit 14 in BIOS Decode Enable register is set
FFF8 0000h-FFFF FFFFh
FFB8 0000h-FFBF FFFFh
LPC or SPI(or PCI)
Always enabled.
The top two 64 KB blocks of this range can be
swapped,as described in Section 4.4.1(Doc#544044)
FF70 0000h-FF7F FFFFh
FF30 0000h-FF3F FFFFh
LPC or SPI(or PCI)
Bit 3 in BIOS Decode Enable register is set
FF60 0000h-FF6F FFFFh
FF20 0000h-FF2F FFFFh
LPC or SPI(or PCI)
Bit 2 in BIOS Decode Enable register is set
FF50 0000h-FF5F FFFFh
FF10 0000h-FF1F FFFFh
LPC or SPI(or PCI)
Bit 1 in BIOS Decode Enable register is set
