47
CM1-86DX3
A.2 I/O Address Map
The SoC positively decodes accesses to all internal registers, including PCI configuration regis-
ters (CF8h and CFCh), PC/AT Compatible IO registers (8237, 8254 & 8259), and all re-locatable
IO space registers (UART).
Table A-1: Fixed IO Ranges in the CPU
Device
IO Address
Comment
DMA 8237-1
0000h – 000Fh
PIC 8259-1
0020h – 0021h
Indirect Access Registers (6117D
configuration port)
0022h – 0023h
Timer Counter 8254
0040h –0043h
Keyboard / Mouse data port
0060h
Port B + NMI control port
0061h
8051 download 4k address counter
0062h – 0063h
Keyboard/ Mouse status/ command
port
0064h
WatchDog0 reload counter
0065h
CMOS RAM port
0070h – 0071h
MTBF control register
0072h – 0075h
DMA page register
0080h – 008Fh
System control register
0092h
PIC 8259-2
00A0h – 00A1h
WatchDog1 control counter
00A8h – 00ADh
WatchDog1 reload counter
00AEh
DMA 8237-2
00C0h – 00DFh
DOS 4G Page access
00E0h – 00EFh
IDE 1(IRQ 15)
0170h – 0177h
COM4 (IRQ 11)
02E8h – 02EFh
COM2 (IRQ 3)
02F8h – 02EFh
COM3 (IRQ 10)
03E8h – 03EFh
IDE1 ATAPI device control write only
register
03F6h
COM1 (IRQ 4)
03F8h – 03FFh
DMA High page register
0480h – 048Fh
Instruction counter register
0490h – 0499h
Instruction counter register
0490h – 0499h
8259 Edge / level control register
04D0h – 04D1h
PCI configuration port
0CF8h – 0CFFh
PCA9535 GPIO Controller
40h
On I2C Bus
The following table shows the variable IO decode ranges. They are
set using base address registers (BARs) or other similar means.
Plug-and-play (PnP) software (PCI/ACPI) can use their configura-
tion mechanisms to set and adjust these values.
