Acromag PMC470 Series User Manual Download Page 6

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SERIES PMC470 PCI MEZZANINE CARD

48-CHANNEL DIGITAL I/O MODULE WITH INTERRUPTS

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purpose. The PMC470 contains the configuration registers, shown
in Table 3.1, to facilitate Plug-and-Play compatibility.

The Configuration Registers are accessed via the Configuration

Address and Data Ports. The most important Configuration
Registers are the Base Address Registers and the Interrupt Line
Register which must be read to determine the base address
assigned to the PMC470 and the interrupt request line that goes
active on a PMC470 interrupt request.

Table 3.1 Configuration Registers

Reg.
Num.

D31 D24

D23 D16

D15 D8

D7 D0

Device ID=5456

Vendor ID= 16D5

Status

Command

Class Code=118000

Rev ID=00

BIST

Header

Latency

Cache

32-bit Memory Base Address for PMC470

4K-Byte Block

5 : 10

Not Used

Subsystem ID=0000

Subsystem Vendor

ID=0000

Not Used

13,14

Reserved

Max_Lat

Min_Gnt

Inter. Pin

Inter. Line

MEMORY MAP

This board is allocated a 4K byte block of memory that is

addressable in the PCI bus memory space to control the input/output
configuration, control, and status monitoring or 48 digital I/O
channels. Each of the I/O points can be configured as either an
input, an output, or an output with readback capability. Interrupt,
event, and debounce capability applies to all 48 channels.

This board operates in two modes: Standard Mode and

Enhanced Mode. Standard Mode provides simple monitor and
control of 48 digital I/O lines. In Standard Mode, each I/O line is
configured as either an input, an output, or an output with readback
capability. Data is read from or written to one of eight groups (ports)
as designated by the address and read and write signals. A Mask
Register is used to disable writes to I/O ports designated as inputs
to prevent possible contention between an external input signal and
the output mosfet. Enhanced Mode includes the same functionality
of Standard Mode, but adds access to 48 additional event sense
inputs connected to each I/O point of ports 0-5 . Thus, the
Enhanced Mode allows event-triggered interrupts to be generated.
Selectable hardware debounce may also be applied in Enhanced
Mode for noise free edge-detection of incoming signals.

Memory is organized and addressed in separate banks of eight

registers or ports (eight ports to a bank). The Standard Mode of
operation addresses the first group of 8 registers or ports (ports 0-5
for reading/writing I/O0-47, Port 6 which is not used, and Port 7
which is the Mask Register). If the Enhanced Mode is selected,
then 3 additional banks of 8 registers are accessed to cover the
additional functionality in this mode. The first bank of the Enhanced
Mode (bank 0) is similar in operation to the Standard Mode. The
second bank (bank 1) provides event sense and interrupt control.
The third bank is used to configure the debounce circuitry to be
applied to input channels in the Enhanced Mode. Two additional
registers are provided to enable the interrupt request line, generate a
software reset, and store the interrupt vector.

The memory space address map for the PMC470 is shown in

Table 3.2. Note the base address for the PMC module must be
added to the addresses shown to properly access the PMC
registers. Registers are 8-bit only and are aligned on a 32-bit
boundry. Thus, the 8-bit registers can be accessed over the PCI
bus via 8-bit, 16-bit, or 32-bit accesses. Note only the lower 8-bits
will contain valid data.

Note that some functions share the same register address. For

these items, the address lines are used along with the read and write
signals to determine the function required.

Standard (Default) Mode Memory Map

The following table shows the memory map for the Standard

Mode of operation. This is the Default mode reached after power-up
or system reset. Standard Mode provides simple monitor and
control of 48 digital I/O lines. In Standard Mode, each I/O line is
configured as either an input, or an output (with readback capability),
but not both. Data is read from or written to one of eight groups
(ports), as designated by the address and read and write signals. A
Mask Register is used to disable writes to I/O ports designated as
input ports. That is, when a port (group of 8 I/O lines) is used as an
input port, writes to this port must be blocked (masked) to prevent
contention between the output circuitry and any external device
driving this line.

To switch to Enhanced Mode, four unique bytes must be written

to port 7, in consecutive order, without doing any reads or writes to
any other port and with interrupts disabled. This is usually done
immediately after power-up or reset. The data pattern to be written
is 07H, 0DH, 06H, and 12H, and this must be written after reset or
power-up.

Table 3.2A: PMC470 R/W Space Address (Hex) Memory Map

HEX
Base
Addr+

MSB

D15 D08

LSB

D07 D00

HEX
Base
Addr+

001

INTERRUPT REGISTER

000

STANDARD MODE (DEFAULT) REGISTER DEFINITION:

201