SERIES PMC470 PCI MEZZANINE CARD
48-CHANNEL DIGITAL I/O MODULE WITH INTERRUPTS
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Enhanced Mode. Remember, the event sense status is a flag that is
raised when a specific positive or negative transition has occurred
for a given I/O point, while the state refers to its current level.
Note that the Interrupt Enable Register at Base A 23CH
is cleared following a power-up or bus initiated software reset. Also,
bit-0 of the Interrupt Register at Base A 000H is not
affected by a software reset. Keep this in mind when you wish to
preserve the information in this register following a reset.
PROGRAMMING EXAMPLE
The following example outlines the steps necessary to configure
the PMC470 for Enhanced Mode operation, to setup event-
generated interrupts, configure debounce, and read and write inputs.
It is assumed that the module has been reset and no prior (non-
default) configuration exists.
For this example, we will configure port 0 I/O points as a four-
channel change-of-state detector. For change-of-state detection,
both positive and negative polarities must be sensed and thus, two
channels are required to detect a change-of-state on a single input
signal. I/O00-I/O03 will be used to detect positive events (low-to-
high transitions), I/O04-07 will be used to detect negative events
(high-to-low transitions). I/O00 and I/O04 will be tied to the first
input signal, I/O01 & I/O05 to the second, I/O02 & I/O06 to the third,
and I/O03 & I/O07 to the fourth. Any change-of-state detected on
these input signals will cause an interrupt to be generated.
1. After power-up or reset, the module is placed in the Standard
Operating Mode. To switch to Enhanced Mode, must write four
unique bytes to the Port 7, Enhanced Mode Select Register at
Base A 21CH, in consecutive order, without doing any
reads or writes to any other ports and with interrupts disabled.
The data pattern to be written is 07H first, followed by 0DH,
followed by 06H, then 12H.
At this point, you are in Enhanced Mode bank 0. Port 7 would
be used to access register banks 1 & 2.
2. Write 80H to the port 7, Bank Status/Select Register at Base
A 21CH to select register bank 2 where debounce will
be configured for our port 0 input channels.
At this point, you are in Enhanced Mode Bank 2 where access
to the debounce configuration registers is obtained.
3. For our example, we want use the 8MHz system clock to
generate our debounce time. By default, the debounce clock is
taken from I/O47 (pin 41 of P1). Select the 8MHz system clock
as the debounce clock by writing 01H to the port 3, Debounce
Clock Select Register at Base A 20CH of this bank.
4. The default debounce duration is 4us with the 8MHz clock
selected in step 3. Write 01H to the port 1, Debounce Duration
Register 0 at Base A 204H of this bank to select a
64us debounce time. An incoming signal must be stable for the
entire debounce time before it will be recognized as a valid input
transition.
Note that Debounce Duration Register 1 (port address 2) would
be used to configure debounce durations for I/O points of ports
4 & 5.
5. Enable the debounce circuitry for port 0 inputs by setting bit 0 of
the Debounce Control Register. Write 01H to the Port 0,
Debounce Control Register at Base A 200 of this bank.
If the module had been configured earlier, you would first read
this register to check the existing settings of debounce enable
for the other ports of this module with the intent of preserving
their configuration by adjusting the value written above.
6. Write 40H to the port 7, Bank Status/Select Register at Base
A 21CH to select register bank 1 where the event
polarity requirements of our application will be configured.
At this point, you are in Enhanced Mode Bank 1 where access
to the event polarity/status registers is obtained.
7. For change-of-state detection, both positive and negative
polarities must be sensed. As such, two channels are required
to detect a change-of-state on a single input signal. For our
example, I/O00-I/O03 will be used to detect positive events (low-
to-high transitions), I/O04-07 will be used to detect negative
events (high-to-low transitions). Write 02H to the port 6, Event
Polarity for Port 0-3 at Base A 218H to set I/O00-I/O03
to positive edge detection, and I/O04-07 to negative edge
detection (Port 4 and 5 I/O channels would use the Port 7
address).
Note that this port address has a dual function depending on
whether a read or write is being executed. As such, if the
current polarity configuration for the other ports must be
preserved, then it must be remembered since it cannot be read
back.
8. To enable event sensing for the port 0 I/O points, write FFH to
the Port 0, Event Sense Clear Register at Base A 200H
for port 0 I/O points in this bank.
Note that writing a 1 to a bit position enables the event sense
detector, while writing a 0 clears the event sensed without
enabling futher event sensing.
9. Write 00H to the port 7, Write Mask Register at Base A
21CH to select register bank 0 where the port 0 input channels
may be write-masked.
Note that the port 7 address bank selection only operates from
bits 6 & 7 of this register, while bits 0-3 are used to select the
event polarity for port 4 & 5 I/O channels. Keep this in mind
when switching banks so as not to inadvertantly change the
polarity configuration of port 4 & 5 input channels in the process
of switching register banks. Likewise, this register has a dual
function depending on whether a read or write is executed. As
such, the polarity settings cannot be read back and must be
remembered if they are to be preserved for successive writes.
At this point, you are in Enhanced Mode Bank 0 where access
to the write-mask register is obtained.
10. For our example, port 0 I/O points are to be used for inputs only
and writes to this port should be masked to prevent the
possibility of data contention between the built-in output circuitry
and the devices driving these inputs. Write 01H to the port 7,
Write Mask Register at Base a 21CH to mask writes to
port 0.
