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       SERIES PMC470 PCI MEZZANINE CARD

        48-CHANNEL DIGITAL I/O MODULE WITH INTERRUPTS

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Enhanced Mode.  Remember, the event sense status is a flag that is
raised when a specific positive or negative transition has occurred
for a given I/O point, while the state refers to its current level.

Note that the Interrupt Enable Register at Base A 23CH

is cleared following a power-up or bus initiated software reset.  Also,
bit-0 of the Interrupt Register at Base A 000H is not
affected by a software reset.  Keep this in mind when you wish to
preserve the information in this register following a reset.

PROGRAMMING EXAMPLE

The following example outlines the steps necessary to configure

the PMC470 for Enhanced Mode operation, to setup event-
generated interrupts, configure debounce, and read and write inputs.
It is assumed that the module has been reset and no prior (non-
default) configuration exists.

For this example, we  will configure port 0 I/O points as a four-

channel change-of-state detector.  For change-of-state detection,
both positive and negative polarities must be sensed and thus, two
channels are required to detect a change-of-state on a single input
signal.  I/O00-I/O03 will be used to detect positive events (low-to-
high transitions), I/O04-07 will be used to detect negative events
(high-to-low transitions).  I/O00 and I/O04 will be tied to the first
input signal, I/O01 & I/O05 to the second, I/O02 & I/O06 to the third,
and I/O03 & I/O07 to the fourth.  Any change-of-state detected on
these input signals will cause an interrupt to be generated.

1.    After power-up or reset, the module is placed in the Standard

Operating Mode.  To switch to Enhanced Mode, must write four
unique bytes to the Port 7, Enhanced Mode Select Register at
Base A 21CH, in consecutive order, without doing any
reads or writes to any other ports and with interrupts disabled.
The data pattern to be written is 07H first, followed by 0DH,
followed by 06H, then 12H.

At this point, you are in Enhanced Mode bank 0.  Port 7 would
be used to access register banks 1 & 2.

2.   Write 80H to the port 7, Bank Status/Select Register at Base

A 21CH to select register bank 2 where debounce will
be configured for our port 0 input channels.

At this point, you are in Enhanced Mode Bank 2 where access
to the debounce configuration registers is obtained.

3.   For our example, we want use the 8MHz system clock to

generate our debounce time.  By default, the debounce clock is
taken from I/O47 (pin 41 of P1).  Select the 8MHz system clock
as the debounce clock by writing 01H to the port 3, Debounce
Clock Select Register at Base A 20CH of this bank.

4.   The default debounce duration is 4us with the 8MHz clock

selected in step 3.  Write 01H to the port 1, Debounce Duration
Register 0 at Base A 204H of this bank to select a
64us debounce time.  An incoming signal must be stable for the
entire debounce time before it will be recognized as a valid input
transition.

Note that Debounce Duration Register 1 (port address 2) would
be used to configure debounce durations for I/O points of ports
4 & 5.

5.   Enable the debounce circuitry for port 0 inputs by setting bit 0 of

the Debounce Control Register.  Write 01H to the Port 0,
Debounce Control Register at Base A 200 of this bank.

If the module had been configured earlier, you would first read
this register to check the existing settings of debounce enable
for the other ports of this module with the intent of preserving
their configuration by adjusting the value written above.

6.   Write 40H to the port 7, Bank Status/Select Register at Base

A 21CH to select register bank 1 where the event
polarity requirements of our application will be configured.

At this point, you are in Enhanced Mode Bank 1 where access
to the event polarity/status registers is obtained.

7.   For change-of-state detection, both positive and negative

polarities must be sensed.  As such, two channels are required
to detect a change-of-state on a single input signal.  For our
example, I/O00-I/O03 will be used to detect positive events (low-
to-high transitions), I/O04-07 will be used to detect negative
events (high-to-low transitions).  Write 02H to the port 6, Event
Polarity for Port 0-3 at Base A 218H to set I/O00-I/O03
to positive edge detection, and I/O04-07 to negative edge
detection (Port 4 and 5 I/O channels would use the Port 7
address).

Note that this port address has a dual function depending on
whether a read or write is being executed.  As such, if the
current polarity configuration for the other ports must be
preserved, then it must be remembered since it cannot be read
back.

8.   To enable event sensing for the port 0 I/O points, write FFH to

the Port 0, Event Sense Clear Register at Base A 200H
for port 0 I/O points in this bank.

Note that writing a 1 to a bit position enables the event sense
detector, while writing a 0 clears the event sensed without
enabling futher event sensing.

9.   Write 00H to the port 7, Write Mask Register at Base A

21CH to select register bank 0 where the port 0 input channels
may be write-masked.

Note that the port 7 address bank selection only operates from
bits 6 & 7 of this register, while bits 0-3 are used to select the
event polarity for port 4 & 5 I/O channels.  Keep this in mind
when switching banks so as not to inadvertantly change the
polarity configuration of port 4 & 5 input channels in the process
of switching register banks.  Likewise, this register has a dual
function depending on whether a read or write is executed.  As
such, the polarity settings cannot be read back and must be
remembered if they are to be preserved for successive writes.

At this point, you are in Enhanced Mode Bank 0 where access
to the write-mask register is obtained.

10.  For our example, port 0 I/O points are to be used for inputs only

and writes to this port should be masked to prevent the
possibility of data contention between the built-in output circuitry
and the devices driving these inputs.  Write 01H to the port 7,
Write Mask Register at Base a 21CH to mask writes to
port 0.

Summary of Contents for PMC470 Series

Page 1: ...nterrupts USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 2000 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 674 C05A002 retired ...

Page 2: ...fe is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility 1 0 GENERAL INFORMATION The PCI Mezzanine Card PMC Series PMC470 has 48 channels of general purpose digital inputs and outputs Inputs and outputs of this module are CMOS and TTL compatible Each of the I O lines can be used as eith...

Page 3: ...g controls for Windows 98 95 ME 2000 and Windows NT compatible application programs Model PMCSW ATX MSDOS format This software provides individual controls that allow Acromag PMC modules to be easily integrated into Windows application programs such as Visual C Visual Basic Microsoft Office 97 applications and others The ActiveX controls provide a high level interface to PMC modules eliminating th...

Page 4: ...models and are directly compatible with industry accepted I O panels termination panels and relay racks Consult the factory for information on compatible products I O Noise and Grounding Considerations The PMC470 is non isolated between the logic and field I O grounds since output common is electrically connected to the PMC module ground Consequently the field I O connections are not isolated from...

Page 5: ... PMC470 is a PCI Local Bus Specification version 2 2 compliant PCI bus target only PMC module The carrier CPU connects a PCI host bus to the PMC module The PCI bus is defined to address three distinct address spaces I O memory and configuration space The PMC module can be accessed via the PCI bus memory space and configuration spaces only The PCI card s configuration registers are initialized by s...

Page 6: ...o cover the additional functionality in this mode The first bank of the Enhanced Mode bank 0 is similar in operation to the Standard Mode The second bank bank 1 provides event sense and interrupt control The third bank is used to configure the debounce circuitry to be applied to input channels in the Enhanced Mode Two additional registers are provided to enable the interrupt request line generate ...

Page 7: ...t 0 Event Sense Clear Register Port 0 I O Points 0 7 200 205 Not Driven 1 READ Port 1 Event Sense Status Reg Port 1 I O Points 8 15 204 205 Not Driven 1 WRITE Port 1 Event Sense Clear Register Port 1 I O Points 8 15 204 209 Not Driven 1 READ Port 2 Event Sense Status Reg Port 2 I O Points 16 23 208 209 Not Driven 1 WRITE Port 2 Event Sense Clear Register Port 2 I O Points 16 23 208 20D Not Driven ...

Page 8: ... this register will return the status of the mask The Mask Register is used to disable writes to I O ports designated as input ports Thus when a port group of 8 I O lines is used for input writes to this port must be blocked masked to prevent contention between the output circuitry open drain and any external devices driving this port Standard Mode Write Mask Register Port 7 BIT WRITE TO REGISTER ...

Page 9: ...p Flop Re enable I O5 Event Sense 6 Port 0 I O6 Event Status Clear I O6 Event Sense Flip Flop Re enable I O6 Event Sense 7 Port 0 I O7 Event Status Clear I O7 Event Sense Flip Flop Re enable I O7 Event Sense Event Interrupt Status Register For Ports 0 5 Enhanced Mode Bank 1 Port 6 Read Only Reading this register will return the event interrupt status of I O ports 0 5 bits 0 5 and the interrupt sta...

Page 10: ...o be monitored and controlled Bank 2 registers control the debounce circuitry of the event inputs Bits 7 and 6 select the bank as follows Bank Selected Status Register Read Bit 7 Bit 6 BANK OF REGISTERS 00 Bank 0 Read Write I O 01 Bank 1 Event Status Clear 10 Bank 2 Event Debounce Control Clock and Duration 11 INVALID DO NOT WRITE BANK 2 REGISTERS Debounce Control Register Enhanced Mode Bank 2 Por...

Page 11: ...wer up or bus initiated software reset will set the outputs to the false high state and place the module in the Standard Operating Mode thus disabling debounce and event detection Pullups on the I O lines ensure a false high input signal for inputs left floating i e reads as 0 A reset will also clear the mask register and enable writes to the I O ports Further all I O event inputs are reset set to...

Page 12: ... negative transitions Since channel polarity is programmable on a nibble basis group of four the first nibble of a port could be configured for low to high transitions the second nibble for high to low transitions As such up to 24 change of state detectors may be configured Debounce Control Debounce control is built into the on board digital ASIC employed by the PMC470 and is enabled in the Enhanc...

Page 13: ...time before it will be recognized as a valid input transition Note that Debounce Duration Register 1 port address 2 would be used to configure debounce durations for I O points of ports 4 5 5 Enable the debounce circuitry for port 0 inputs by setting bit 0 of the Debounce Control Register Write 01H to the Port 0 Debounce Control Register at Base Address 200 of this bank If the module had been conf...

Page 14: ... the PMC module will initially terminate with a retry While the read data is moved to the read register typically 1000ns continued retries will result in retry terminations The retry termination allows the PCI bus to be free for other system operations while the data is moved to the read register A PCI bus write to the PMC module will result in 1 immmediately accepting the write data and normal cy...

Page 15: ...V direct contact discharge at input output terminals and European Standard EN50082 1 Electric Fast Transient Immunity EFT Complies with IEC1000 4 4 Level 2 0 5KV at field input and output terminals and European Norm EN50082 1 Radiated Emissions Meets or exceeds European Norm EN50081 1 for class A equipment Warning This is a class A product In a domestic environment this product may cause radio int...

Page 16: ... feet This shielded cable is recommended for all I O applications both digital I O and precision analog I O Application Used to connect Model 5025 552 termination panel to the PMC Module Length Standard lenght is 2 meters 6 56 feet Consult factory for other lenghts It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 50 conductors 28 AWG on 0 050 inch center...

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