AP513 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 41 -
http://www.acromag.com
- 41 -
www.acromag.com
read. Only one “0” character is loaded into the
FIFO when the break occurs.
5
Transmit
FIFO Empty
0 = Not Empty
1 = Empty
–
indicates that the transmitter is
ready to accept a new character for
transmission. The last data byte has been
transferred from the transmit FIFO to the
transmit shift register.
6
Transmitter
Empty
0 = Not Empty
1 = Transmitter Empty
–
set when
both the transmit FIFO (or THR, in non-FIFO
mode) and the Transmit Shift Register (TSR) are
both empty.
7
Receiver
FIFO Error
0 = No Error in FIFO (default).
1 = Error in FIFO
–
An indicator for the sum of all
error bits in the Rx FIFO. At least one parity
error, framing error or break indication is in the
FIFO data. Cleared when there are no more
errors in the FIFO.
Note that LSR Bits 1-4 are the error conditions that produce a receiver-line-
status interrupt (a priority 1 interrupt in the ISR register when any one of
these conditions are detected). This interrupt is enabled by setting IER bit 2
to “1”.
A power-up or system reset sets all LSR bits to 0, except bits 5 and 6 which
are high.
3.4.10 Modem Status Register (MSR)
–
Read Only
The Modem Status Register (MSR) provides the host CPU with an indication
on the status of the modem input line from a modem or other peripheral
device. This register allows the current state of CTS to be read (bit 4) and
provides indication on whether the states of the lines has changed since the
last read of the MSR (bit 0 is set high when the corresponding control input
changes state and is reset low when the CPU reads the MSR).
Table 3.18 Modem Status Register
MSR
BIT
FUNCTION
0
CTS - Set if CTS# has changed states since last read of MSR.
A modem status interrupt will be generated if MSR interrupt
is enabled (IER bit[3]).
