SERIES AP441 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 21 -
http://www.acromag.com
- 21 -
www.acromag.com
7 to 3
Module Slot Location Bits. These bits identify the slot location
of the AP module in a system. The Carrier may use backplane
signals as in a VPX system or an on-carrier DIP switch to
uniquely identify the system location of the carrier.
XXXXX
System Slot identification bits are described by the
AcroPack carrier card.
31 to 8 Not Used
Input Port X Registers (Read)
(BAR0 + 0x0000 0008 –
0x0000 0014)
Four registers are provided to monitor 32 possible input points. Data is read
from one of four groups of eight I/O lines, as designated by the address and
read and write signals. A read of this register returns the status (ON/OFF) of
the input point. Bit 0 of each register corresponds to the lowest numbered
I/O point, while Bit 7 corresponds to the highest numbered I/O point.
Event Enable Registers (Read/Write)
(BAR0 + 0x0000 0018 –
0x0000 0024)
The Event Enable Registers provide a mask bit for each of the 32 possible
interrupt channels. A “0” bit will prevent the corresponding input channel
from detecting an event. A “1” bit will allow the corresponding input
channel to detect events as configured by the Event Type and Event Polarity
Control Registers. Bit 0 of each register corresponds to the lowest numbered
I/O point, while Bit 7 corresponds to the highest numbered I/O point.
If both an Event Sense and the board Interrupt Enable bit is set, then
interrupts can be generated.
Event Type (COS or H/L) Configuration Registers (Read/Write)
Event Polarity Control Registers (Read/Write)
(BAR0 + 0x0000 0038 –
0x0000 0044)
A write to these registers controls the polarity of the input sense event for
each channel. A “1” written to a bit in these registers will cause the
corresponding event sense input channel to flag positive events (low-to-high
transitions). A “0” will cause negative events to be sensed (high-to-low
(BAR0 + 0x0000 0028 –
0x0000 0034)
The Event Type Configuration Registers determine the type of input channel
transition that will generate an event for each of the thirty-two possible
event sensing channels. A “0” bit selects event on level transition. An event
will be generated when the input channel level specified by the Event
Polarity Register occurs (i.e. low or high-level transition event). A “1” bit
means the event will occur when a Change-Of-State (COS) occurs at the
corresponding input channel (i.e. any state transition, low to high or high to
low). Bit 0 of each register corresponds to the lowest numbered I/O point,
while Bit 7 corresponds to the highest numbered I/O point.
Note that no events will be detected until enabled via the Event Enable
Register. Further, interrupts will not be reported to the system unless the
Interrupt enable bit-0 has been configured for enable via the Interrupt
Register. All bits are set to “0” following a reset which means that, if
enabled, the inputs will cause events and/or interrupts for the levels
specified by the Event Polarity Register.
