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Acqiris SA240P, User Manual

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1.5   Trigger

16

Acqiris SA240P User's Manual

Edge trigger slope

The trigger slope defines which one of the two possible transitions will be used to initiate the trigger
when it passes through the specified trigger level. Positive slope indicates that the signal is
transitioning from a lower voltage to a higher voltage. Negative slope indicates the signal is
transitioning from a higher voltage to a lower voltage.

Trigger delays

For more details about triggers modes, post/pre-trigger delays and time-stamps, see

Trigger modes

and time-stamps (page 54)

.

Summary of Contents for SA240P

Page 1: ...Acqiris SA240P Acquisition Card 2 channels 14 bit 4 GS s DC up to 2 GHzbandwidth User s Manual ...

Page 2: ...ior agreement and written consent from Acqiris SA as governed by international copyright laws Version June 2021 Contact us Acqiris Americas contact americas acqiris com Acqiris Europe contact emea acqiris com Acqiris Asia Pacific contact asia pacific acqiris com Acqiris Japan contact japan acqiris com Worldwide contact for support support acqiris com Acqiris SA Chemin des Aulx 12 1228 Plan Les Oua...

Page 3: ... configurable options 7 Main Card Features 8 1 1 SA240P front panel features 9 1 2 Channel input specifications 10 1 3 Sampling and data acquisition 12 1 4 Calibration 13 1 5 Trigger 15 Signal Acquisition Modes and Real Time Processing 17 2 1 Digitizer acquisition mode 18 2 2 Real time averaging mode AVG option 22 Readout Modes 29 3 1 Standard readout modes 29 3 2 Simultaneous acquisition and read...

Page 4: ...4 7 4 How to access repeated capabilities 75 7 5 How to generate a software trigger 76 7 6 How to enable or bypass the bandwidth limiter 77 7 7 How to set the external trigger 78 7 8 How to perform binary decimation depending on firmware 79 Software utilities 80 8 1 ADC card Verification Utility AqMD3Verify 80 FAQ 82 9 1 Q What is coherent sampling 82 9 2 Q How to manage the internal temperature 8...

Page 5: ...cellent signal fidelity across a wide bandwidth This new card and module generation with advanced real time processing capabilities is designed for embedded OEM applications in a variety of challenging measurements imaging and processing systems Product description The SA240P ADC card is the 4 GS s and dual channel version of the SA2 product family This unique DC coupled 14 bit digitizer captures ...

Page 6: ...d occupies a single PCIe slot offering high performance in a small footprint All the ADC cards and modules from the SA2 family implement a proprietary low noise front end With undisputed spurious free dynamic range SFDR and signal noise ratio SNR performances in high frequencies it is ideal for OEM applications requiring digitizer sampling at wide bandwidth and very high dynamic range especially a...

Page 7: ...fer to the SA240P datasheet Product configurable options The SA240P comes with several options Additional memory 4 GB MEA option 8 GB MEB option ADC Card modes Digitizer mode DGT Real time averaging AVG option Optional features Simultaneous acquisition and readout Streaming records CST option Zero Supress Thresholding ZS1 option Custom firmware capability CFW option Other internal references I O p...

Page 8: ...d Features 8 Acqiris SA240P User s Manual Chapter 1 MainCard Features 1 1 SA240P front panel features 9 1 2 Channel input specifications 10 1 3 Sampling and data acquisition 12 1 4 Calibration 13 1 5 Trigger 15 ...

Page 9: ...nal programmable 50 Ω source LVCMOS 3 3 V I O 1 2 3 MMCX User configurable digital Input Output signal DC coupling LVCMOS 3 3 V Output 50 Ω source Input 5 V max REF IN MMCX External reference clock input AC coupled and 50 Ω terminated It can accept a 10 MHz or a 100 MHz signal from 3 to 3 dBm Table 1 1 List of SA240P front panel IOs The ADC card can usually work with signal present at the external...

Page 10: ...imized for a target voltage page 71 Impedance coupling The input channel termination is 50 Ω The input coupling is DC Input protection The input amplifiers are designed to accept signals within the absolute maximum operating voltages shown in the table Bandwidth and rise time The bandwidth specification indicates the frequency at which an input signal will be attenuated by 3 dB approximately 30 lo...

Page 11: ...ability at 20 MHz 200 MHz or 700 MHz Also see Programing section How to enable or bypass the bandwidth limiter page 77 Vertical resolution The SA240P uses 14 bit ADCs giving 16384 levels at each input full scale range i e 16384 level of 61 μV average width when using the 1 V FSR or 30 μV using the 500 mV FSR See Acquired data format page 20 for more details ...

Page 12: ...bits Single or multi record up to 131 072 records or continuous steaming with CST option Table 1 3 Acquisition sampling rate and resolution per channel Data acquisition modes and functions The SA240P ADC card supports several acquisition modes and optional functions for real time signal processing in FPGA You can refer to the corresponding section for details ADC card modes Digitizer acquisition m...

Page 13: ...0 minutes of ADC card operation after power on A full internal calibration of a ADC card can be time consuming because of the many possible configuration states Therefore the self calibration is performed only for the current configuration state and is mandatory before making the first acquisition with given settings Indeed the AqMD3 driver prevents an acquisition from being performed unless a sel...

Page 14: ... INMETRO BIPM etc The measured performance is then compared to published datasheet specifications For each factory calibration Acqiris tests the performance corresponding to all datasheet specifications for every installed option If needed the DUT is adjusted and re qualified ensuring it is in line with full specifications Our ADC cards are calibrated at factory during the production phase There i...

Page 15: ...mpedance with DC coupling Trigger input bandwidths The bandwidth depends on the trigger source Channel trigger The 3 dB bandwidth of the comparator of the channel triggers is from DC to 2 5 GHz External trigger The external trigger input has a bandwidth from DC to 3 GHz Refer to section How to set the external trigger page 78 for additional information Trigger level The trigger level specifies the...

Page 16: ... it passes through the specified trigger level Positive slope indicates that the signal is transitioning from a lower voltage to a higher voltage Negative slope indicates the signal is transitioning from a higher voltage to a lower voltage Trigger delays For more details about triggers modes post pre trigger delays and time stamps see Trigger modes and time stamps page 54 ...

Page 17: ...zed for each application and eventually for each of your system This section details the acquisition modes 2 1 Digitizer acquisition mode 18 2 2 Real time averaging mode AVG option 22 The modes available with your product depends on the firmware options ordered with your products To check which options and mode are present on your ADC card you can use the MD3 Software Front Panel from the Windows ...

Page 18: ...e same time to within a small fraction of the maximum sampling rate The single record acquisition mode is the normal operation of most ADC card products In this mode an acquisition consists of a waveform recorded with a single trigger The user selects the sampling rate and record size and sets the number of records to 1 default value For details about the trigger sources see Trigger page 15 Figure...

Page 19: ...e maximum number of records is 128k Program examples for single record or multi records acquisitions are available C Program Files IVI Foundation IVI Drivers AqMD3 Examples Acquisition memory Data from the ADC is stored in on board acquisition memory The amount of memory in use for acquisition can be programmed and is selectable from 1 point to the full amount of acquisition memory available Model...

Page 20: ...x sampling rate Max recording time window at higher sampling rate SA240 MEA default 4 GB 4 GS s 250 ms on 2 channels 500 ms on 1 channel MEB optional 8 GB 500 ms on 2 channels 1 s on 1 channel Table 2 2 Maximum recorded time at maximum sampling rate depending on ordered memory option Maximum acquisition time There is a limit on the acquisition time acquisition length in digitizer mode depending on...

Page 21: ...ctions all 16 bits should be considered when using the samples values in ADC code format Using basic digitizer function without DGT option If the ADC card had been ordered with a specific application mode and without the digitizer mode i e without DGT firmware option user can perfom the basic digitizer functions described in previous sections but with restriction for the following features Limitat...

Page 22: ...Averaging from 1 up to 65 536 triggers in steps of 1 trigger Effective acquisition length up to 512k per channel or 1M Samples when using only the chan nel 1 while disabling channel two Noise suppressed accumulation NSA Self Trigger mode for minimal synchronous pattern noise Baseline stabilization algorithm and digital offset Decimation factors of 2 4 8 16 or 32 with associated low pass filters en...

Page 23: ...mainly on the PCIe connection and CPU multitasking activity The time to initiate the next acquisition The function simultaneous acquisition and readout CST can be combined with the averager mode removing the above limitation and reducing the time between averaging sequences See Averager with simultaneous acquisition and readout AVG CST page 41 Noise suppressed accumulation NSA In some applications...

Page 24: ...se base is subtracted from data values which are higher than the configured threshold This parameter is defined as signed left aligned 16 bit ADC code and in the range of Threshold 32767 Threshold if Threshold 0 Threshold Threshold 32768 if Threshold 0 Sequence When enabling the NSA the recommended sequence is the following 1 Configuring the channel and acquisition parameters voltage range offset ...

Page 25: ...SourceSelfTriggerSquareWave Interface Specifies the frequency of the Self Trigger square wave signal The units are Hertz DutyCycle IAqMD3TriggerSourceSelfTriggerSquareWave Interface Configures the duty cycle of the Self Trigger square wave signal Units are percentage of the period Slope IAqMD3TriggerSourceSelfTriggerSquareWave Interface Specifies whether a rising or a falling edge of the generated...

Page 26: ...selected by setting IAqMD3Acquisition Mode property to Acqiris AqMD3 AcquisitionMode Averager instrument Acquisition Mode AcquisitionMode Averager IVI C The attribute AQMD3_ATTR_ACQUISITION_MODE ViInt32 must be set to value AQMD3_VAL_ ACQUISITION_MODE_AVERAGER AqMD3_SetAttributeViInt32 session AQMD3_ATTR_ACQUISITION_MODE AQMD3_VAL_ACQUISITION_MODE_AVERAGER Program examples for acquisitions with re...

Page 27: ...tion in Averager or Peak Detection mode Returned waveform data units are Volts Attributes Attribute Description AQMD3_ATTR_ ACQUISITION_MODE The acquisition mode i e Averager AQMD3_ATTR_ ACQUISITION_NUMBER_ OF_AVERAGES Specifies the number of waveforms to average in the record This attribute affects card behavior only when the Acquisition Mode attribute is set to Aver ager or PeakDetection AQMD3_A...

Page 28: ...cted from data values which are higher than the configured threshold The units are ADC counts Threshold Specifies the threshold of the Noise Suppressed Accumulation Each data value must exceed the threshold value to be entered into the sum The units are ADC counts IAqMD3ChannelMeasurement FetchAccumulatedWaveformInt32 This function returns the accu mulated waveform which the ADC card has acquired ...

Page 29: ...n and readout modes are Single record mode one shot with single waveform with a single trigger Multi record mode one shot with multiple waveforms with multiple triggers Figure 3 1 Acquisition sequence using a single record Figure 3 2 Acquisition sequence using multi records The specific readout mode s detailed in the following depends on your product version and ordered options ...

Page 30: ...s section focuses on the usage of simultaneous acquisition and readout in digitizer mode The next section presents the Averager with simultaneous acquisition and readout AVG CST page 41 In a standard readout mode acquisition and readout are sequential the readout of the data is performed after the acquisition has stopped Consequently the duration of the acquisition is limited by the ADC card inter...

Page 31: ...pipe represents the volume of data flow that can be extracted from the card When the stream data rate is larger than the available PCIe data bandwidth an overflow occurs and the acquisition stops Figure 3 4 Illustration of the data stream concept Usage Acquisition User should define the record size the number of samples per record should be a multiple of 32 the number of elements to fetch should b...

Page 32: ... This number is always numElementsToFetch firstValidElement represents the first valid Int32 element in the returned data buffer It is used for data alignment reasons elements contains the int32 data returned by the function When fetching the data stream each int32 contains two 14 bit raw data mapped on 16 bits and left aligned For example element 0 contains sample_0 and sample_1 element 1 contain...

Page 33: ...ws to truncates the samples to fewer bits and packs them continuously on 12 bit instead of 16 bit to reduce the total volume of data The truncation is disabled by default and can be enabled using AQMD3_ATTR_STREAM_SAMPLES_ DATA_TRUNCATION_ENABLED IVI C attribute or DataTruncationEnabled from IAqMD3StreamSamples IVI NET interface ...

Page 34: ...3 2 Simultaneous acquisition and readout CST option 34 Acqiris SA240P User s Manual Acquisition sequence An example of CST acquisition sequence is illustrated below Figure 3 5 CST acquisition sequence ...

Page 35: ... read is performed Data buffer allocation For data buffer ViInt64 sampleStreamGrain 0 checkApiCall AqMD3_GetAttributeViInt64 session sampleStreamName AQMD3_ATTR_STREAM_GRANULARITY_IN_ BYTES sampleStreamGrain ViInt32 const alignmentOverhead ViInt32 sampleStreamGrain sizeof ViInt32 1 vector ViInt32 sampleElements nbrSampleElementsToFetch alignmentOverhead nbrSampleElementsToFetch 2 data alignment da...

Page 36: ...river The CST acquisition mode may be enabled by setting the Streaming Mode to Triggered To stop the streaming mode an Abort should be performed The different streams are implemented as instances of stream Repeated capabilities There are several types of stream Repeated capabilities Detailed help may be found in AqMD3 IVI Driver Help Please refer to AqMD3 chm IVI C or Acqiris AqMD3 Fx40 chm IVI NE...

Page 37: ...3 2 Simultaneous acquisition and readout CST option Acqiris SA240P User s Manual 37 IVI NET ...

Page 38: ...gth This mode sup ports an unlimited number of triggered records depending on record size and trigger rate IAqMD3Streams Count Indicates the number of stream repeated capabilities Name Indicates the stream name for a given index FetchDataInt32 This function returns a stream of Elements The ElementSizeInBits and the meaning of each Element depend on the StreamType Enabled Specifies whether the stre...

Page 39: ...onEnabled is False DataTruncationKeepMsb Specifies whether the output stream Element contains the most significant or the least significant bits of the raw ADC card data sample Ignored if DataTrun cationEnabled is False IVI C Function AqMD3_StreamFetchDataInt32 This function returns a stream of Elements The Ele mentSizeInBits and the meaning of each Element depend on the StreamType AqMD3_GetStream...

Page 40: ...card AQMD3_ATTR_STREAM_TYPE Indicates the type of the stream AQMD3_ATTR_STREAM_GRANULARITY_IN_ BYTES Indicates the granularity of data for the FetchData oper ations AQMD3_ATTR_STREAM_MAX_SIZE_IN_BYTES Indicates the maximal size of data for the FetchData oper ations AQMD3_ATTR_STREAM_MARKERS_BITS_PER_ MARKER Indicates the number of bits representing a Marker value AQMD3_ATTR_STREAM_MARKERS_ FRACTIO...

Page 41: ... see detail in section Real time averaging mode AVG option page 22 The addition of simultaneous acquisition and readout feature CST on top of real time averaging enables minimal dead time between accumulations Functional description The architecture is based on simultaneous acquisition and readout CST and enables simultaneous real time averaging and transfer of accumulated records to host processo...

Page 42: ... Thanks to CST mode high data rate can be sustained without losing any trigger The number of averages for an accumulation sequence can be selected from 1 up to 65k triggers When the abort command occurs the ongoing partial accumulated record cannot be read Acquisition sequence First user should configure the averager Accumulation settings and features are the same as standard AVG Then CST mode has...

Page 43: ... CST Acqiris SA240P User s Manual 43 Figure 3 7 AVG CST acquisition sequence Performance Excepted for small number of averages the architecture enables no trigger loss The maximum performance of the system depends on the number of averages and the trigger rate ...

Page 44: ...rocessing features that can be enable e g to optimize signal performance or reduce data volume depending on each application These features are common to the acquisition modes excepted when specified differently 4 1 Baseline stabilization and digital offset 45 4 2 Sampling rate reduction binary decimation 48 4 3 Data inversion 49 4 4 Equalization 50 ...

Page 45: ...tion example Principle The baseline stabilization or baseline correction is not enabled by default When activated the baseline stabilization algorithm consists in the main following steps 1 Baseline estimation The estimated baseline is iteratively adapted to the input data The baseline is estimated from samples of the incoming input data except when a pulse is detected 2 Baseline correction The es...

Page 46: ... i e from the trigger to the end of the record defined by acquisition size This mode is a way to exclude unwanted signal values from the baseline estimation assuming that there is no or very low active signal outside the acquisition window Configuration The interfaces methods properties functions attributes listed below are provided by the Acqiris MD3 Software Detailed help on these interfaces may...

Page 47: ...old as signed left aligned 16 bit ADC code The threshold is applied to the stabilized signal before DigitalOffset addi tion i e relative to 0 IVI NET Interface Method Property name Description IAqMD3ChannelBaselineCorrection Configure Configures the baseline stabilization properties DigitalOffset Applies a digital offset after the baseline correction DigitalOffset is a signed left aligned 16 bit A...

Page 48: ...imation user should set the sampling rate to required decimated sampling rate Decimation and bandwidth limitation The table below provides the behavior when combining decimation and bandwidth limitation Decimation factor Effective sampling rate Bandwidth typical bandwidth filter applied vs Bandwidth limited BWL None BWL 700 MHz BWL 200 MHz BWL 20 MHz 1 4 GS s 2 GHz No filter BWL 700 MHz BWL 200 MH...

Page 49: ...r or real time averaging modes When enabled the signal inversion is applied before the NSA settings or the signal thresholding Configuration IVI C Attribute Description AQMD3_ATTR_CHANNEL_ DATA_INVERSION_ ENABLED Specifies whether the data acquired is inverted IVI NET Interface Method Property name Description IAqMD3Channel DataInversionEnabled Specifies whether the data acquired is inverted ...

Page 50: ...ectrum monitoring It is also possible to implement a user custom equalization depending on your application To proceed please contact factory support acqiris com By default Custom Equalization is equivalent to Equalization Off The equalization option is supported for both digitizer DGT and averager AVG modes Driver property attribute The equalization mode can be selected as detailed below Driver A...

Page 51: ...ge requirements and to the resulting clipped sample data the default driver behavior is to return an error in such a condition Note that the acquired data are still available for read see example below It is also possible to disable the overrange detection Due to the internal ADC frequency response superior to 0 dB for high frequencies see above the Bode plot without equalization there is a risk o...

Page 52: ..._ OVERRANGE_ENABLED When set to true all Fetch and Read methods will return an error if the ADC was in overrange i e some samples are outside of the numeric range of the ADC output Default is true IVI NET IAqMD3Acquisition ErrorOnOverrangeEnabled Driver Error Description IVI C AQMD3_ERROR_ADC_OVERRANGE ADC is in overrange acquisition data is invalid IVI NET Acqiris AqMD3 AdcoverrangeException Exam...

Page 53: ...d Synchronization Acqiris SA240P User s Manual 53 Chapter 5 Controland Synchronization 5 1 External reference 54 5 2 Trigger modes and time stamps 54 5 3 Trigger output 59 5 4 Multi purpose inputs and outputs 61 ...

Page 54: ...ified value you must remember to compensate for the difference in your application since the ADC card and the driver have no way to know about such deviations Parameter Value Tolerance Nominal Frequency 100 MHz or 10 MHz 1 kHz Signal level 3 dBm to 3 dBm Impedance 50 Ω Coupling AC Minimum ampliture 440 mVpp sinus Maximum power 2 mW Maximum voltage 900 mVpp sinus Table 5 1 External reference specif...

Page 55: ...features baseline stabilization zero suppress ZS1 data inversion capability or simultaneous acquisition and readout CST Figure 5 1 Acquisition timeline depending on the trigger delay defined Trigger delay parameter Digitizer acquisition mode The amount of pre trigger delay can be adjusted between 0 and 100 of the acquisition time window thus the minimum trigger delay is given by 1 Record size Samp...

Page 56: ...e a negative number The trigger delay granularity is less than one sample interval 0s Averager acquisition mode In this mode the pre trigger delay is not supported Thus the minimum trigger delay is 0s The maximum trigger delay is given by 224 1 16 SamplingRate The trigger delay granularity is given by 16 SamplingRate Trigger time interpolator and time stamps The trigger time stamp is the trigger a...

Page 57: ... relative to anything or the relative measure is zero or the waveform is empty EndTime EndTime is the time between the last valid data point in the waveform and the TriggerTime Positive values of EndTime indicate that it occurred after the trigger If EndTime is zero there is exactly one data point and the StartTime is zero or the waveform is empty TotalTime TotalTime is the timespan represented by...

Page 58: ...any specific demand relative to this limitation or to self trigger Parameters ActiveSource IAqMD3Trigger ActiveSource property Specifies the trigger source There are three trigger sources internal external and self trigger If the Self Trigger mode is selected the Self Trigger parameters should be set and the IO 3 output should be enabled Frequency IAqMD3TriggerSourceSelfTriggerSquareWave Interface...

Page 59: ...b multiple of sample clock is sent to the Trigger Out TriggerCompare The trigger input condition has been satisfied but not necessarily triggered e g the trigger enable was not asserted SelfTrigger See Self trigger mode page 25 Table 5 2 List of supported trigger out signals Trigger output signal behavior By default the trigger output is LowLevel If selecting a trigger output source e g TriggerAcc...

Page 60: ...en terminated on 50 Ω The maximum output current capability is 15 mA As the output is retro terminated it is possible to drive a 50 Ω line un terminated HiZ without loss of performance Figure 5 2 Trigger output block diagram The external trigger output functionality is implemented in the hardware No trigger out signal occurs for software generated triggers ...

Page 61: ...ition is ongoing AVG IO 3 only Out LowLevel Level Fixed low level signal for debug purposes Out HighLevel Level Fixed high level signal for debug purposes Table 5 3 List of signals selectable for the programmables I Os The list of Available signals is indicated as a comma separated list by member IAqMD3ControlIO AvailableSignals IVI NET or attribute AQMD3_ATTR_CONTROL_IO_ AVAILABLE_SIGNALS IVI C S...

Page 62: ... typically give 1 6 V into 50 Ω As can be seen in the diagram below the 3 3 V output buffer has a 50 Ω resistor in series Therefore the available output high level voltage will depend on the load applied In the example below a 50 Ω termination will result in a nominal high level of 1 6 V Vo Rload 50 Rload 3 3 Figure 5 4 Output equivalent circuit ...

Page 63: ...s Visual C LabWindow CVI LabVIEW MATLAB IVI NET Driver The AqMD3 IVI NET driver can be used in the following development environments Visual C Visual C CLI Visual Basic NET Driver API documentation The AqMD3 APIdocumentation can also be accessed from IVI C Start Acqiris MD3 Documentation AqMD3 C IVI Driver Version Documentation IVI NET Start Acqiris MD3 Documentation AqMD3 NET IVI Driver Version D...

Page 64: ...brary lib must be referenced This section demonstrates usage of the driver using instrument specific references All IVI C driver programs must do the following include AqMD3 h Link to AqMD3 lib Prefix function calls with AqMD3_ To use the AqMD3 specific driver perform the following steps in Visual Studio 1 In solution explorer right click on the project and choose Properties 2 In the property page...

Page 65: ...eset VI_FALSE Setup IVI defined initialization options ViConstString standardInitOptions Cache true InterchangeCheck false QueryInstrStatus true RangeCheck true RecordCoercions false Simulate false status AqMD3_InitWithOptions PXI40 0 0 INSTR idQuery reset standardInitOptions session status AqMD3_close vi Accessing Attributes Accessing attributes in an IVI C driver is accomplished via a set of IVI...

Page 66: ... from MD2 2 x to MD3 3 x Please refer to the following documents for guidelines accessible from Start Acqiris MD3 Documentation or from C Program Files Acqiris MD3 Documentation AgMD2 to AqMD3 IVI C Software Migration Note pdf AgMD2 IVI COM to AqMD3 IVI NET Software Migration Note pdf ...

Page 67: ... Bypass false By default the bandwidth limiter is disable Vertical range 1 Volts Vertical offset 0 Volts Vertical coupling DC Trigger source Internal1 Trigger delay 0 ns Trigger type Edge Trigger coupling DC Trigger level 0 Volts Trigger slope Positive Interleave Disable Mode Normal DGT Sampling rate 4 GS s Sample clock Internal Reference oscillator Internal Reference oscillator frequency 10 MHz F...

Page 68: ...ctual action Actions with implicit ApplySetup Method name Description SelfTest To insure the card is actually in the desired state before doing the self test SelfCalibrate To insure the card is actually in the desired state before self calibrating Initiate To apply the configured setup to the card hardware before starting the measurement Read All Read methods start by performing an Initiate follow...

Page 69: ...librate the card 71 7 3 How to configure and read data on two channels 74 7 4 How to access repeated capabilities 75 7 5 How to generate a software trigger 76 7 6 How to enable or bypass the bandwidth limiter 77 7 7 How to set the external trigger 78 7 8 How to perform binary decimation depending on firmware 79 ...

Page 70: ...r the PXI instruments on user system and get their VISA addresses include stdio h include visa h int main ViSession rm VI_NULL viOpenDefaultRM rm ViChar search PXI INSTR ViFindList find VI_NULL ViUInt32 count 0 ViChar rsrc 256 ViStatus status viFindRsrc rm search find count rsrc if status VI_SUCCESS count 0 do printf Found s n rsrc status viFindNext find rsrc while status VI_SUCCESS viClose find e...

Page 71: ...The smart calibration implemented in MD3 drivers allows to save time by automatically keeping in memory the calibration information from any self calibration performed since the beginning of the session When the acquisition parameters are changed no re calibration of the card is necessary if a self calibration has already been performed with the same acquisition conditions i e the same set of para...

Page 72: ...st time for an identical set of parameter values Channel parameters Vertical range Input filter Bypass Yes No CalibrationTargetVoltage Only if Calibration TargetVoltageEnabled is true And each time this parameter changes Offset B Trigger Trigger source Only the 1st time C External reference Reference mode External or Internal Reference Each time this parameter changes The channel parameters are ca...

Page 73: ...7 2 How to calibrate the card Acqiris SA240P User s Manual 73 IVI NET Interface Method Property name IAqMD3Calibration IsRequired SelfCalibrate ...

Page 74: ...instance Fetch acquired data Giving a null pointer as data array to the fetch function means the driver will allocate the proper amount of memory during the fetch call Ivi Digitizer IWaveformCollection Int16 waveformsCh1 null Ivi Digitizer IWaveformCollection Int16 waveformsCh2 null waveformsCh1 driver Channels Channel1 MultiRecordMeasurement FetchMultiRecordWaveform firstRecord numRecords offsetW...

Page 75: ...Link Not supported LogicDeviceMemoryBank Not supported MonitoringValue These parameters are for information only or can be used for debugging purpose There are accessible through the MD3 SFP or the command below Please refer to AqMD3 chm IVI C or Acqiris AqMD3 Fx40 chm IVI NET Stream streamCh1 MarkersCh1 streamCh2 MarkersCh2 The number of instances and their names however can be queried from the d...

Page 76: ...oftwareTrigger IVI C or to method IAqMD3Trigger SendSoftwareTrigger IVI NET sends a single software trigger SendSoftwareTrigger must be called as many times as required Multi record acquisitions required a trigger per record Accumulated records require a trigger per accumulation SendSoftwareTrigger needs to be called for each trigger event ...

Page 77: ...TR_INPUT_FILTER_BYPASS VI_TRUE Using the AqMD3 IVI NET driver driver Channels L Channel1 Filter Bypass true Selecting the filter frequency User can select the desired the Max frequency by setting Channels Filter MaxFrequency Both Channel1 and Channel2 must have the exact same filter configuration Using the AqMD3 IVI C driver ins Channels Channel1 Filter Bypass false ins Channels Channel2 Filter By...

Page 78: ...IVI C AqMD3_SetAttributeViString session AQMD3_ATTR_ACTIVE_TRIGGER_SOURCE External1 AqMD3_SetAttributeViReal64 session External1 AQMD3_ATTR_TRIGGER_LEVEL level IVI NET spDriver Trigger ActiveSource External IAqMD3TriggerSourcePtr spTrigSrc spDriver Trigger Sources Item L External1 spTrigSrc Level level in volts The different trigger sources are listed in the section How to access repeated capabili...

Page 79: ...lease refer to section for more information Using the AqMD3 IVI C driver To use the binary decimation and set the sample rate to a lower value use the AQMD3_ATTR_ SAMPLE_RATE attribute sampleRate 200e6 status AqMD3_SetAttributeViReal64 session AQMD3_ATTR_SAMPLE_RATE sampleRate Using the AqMD3 IVI NET driver To use the binary decimation and set the sample rate to a lower value use the SampleRate pr...

Page 80: ...e signal with reference signal expected val ues This utility checks the version of control FPGA firmware already loaded If necessary it pro poses to update the firmware using the Firmware Update Utility You can launch AqMD3Verify from the start menu AqMD3Verify requests the user to connect a reference signal and then to press any key to continue as shown in the window below AqMD3Verify checks the ...

Page 81: ...erify Acqiris SA240P User s Manual 81 When the version of control FPGA firmware is updated and successful please power off your computer restart it again for the update to take effect and process AqMD3Verify tool as described in this section ...

Page 82: ...t frequency close to Fs 2 let s say Fin 44 MHz then Ncycles 901 12 which is close to an integer We could therefore round down to Ncycles 901 and we would get Fin 43 994140625 MHz which is an input frequency that satisfies coherent sampling The integer number should be chosen carefully We have three possible types of integers even odd and prime Even is not a good idea since we would hit the same co...

Page 83: ... reach 100 C in standard operating mode which is within the components operating conditions This parameter is provided for information only 9 3 Q What happens if the host processor goes in hibernation mode A Hibernation while the ADC card is in operation is not supported Recommendation is to close the ADC card before the host computer is allowed to go into hibernation There are many situations whe...

Page 84: ...electric shock and contact with hazardous live circuits Service personnel are trained to work on live circuits perform safe installations and repair products Only properly trained service personnel may perform installation and service procedures Operator is responsible to maintain safe operating conditions To ensure safe operating conditions cards should not be operated beyond the full temperature...

Page 85: ...ator For maximum safety do not touch the product test cables or any other instruments while power is applied to the circuit under test ALWAYS remove power from the entire test system and discharge any capacitors before connecting or disconnecting cables or jumpers installing or removing ADC cards or making internal changes such as installing or removing jumpers Do not touch any object that could p...

Page 86: ...mark of the European Community Australian Communication and Media Authority mark to indicate regulatory compliance as a registered supplier This symbol indicates product compliance with the Canadian Interference Causing Equipment Standard ICES 001 It also identifies the product is an Industrial Scientific and Medical Group 1 Class A product CISPR 11 Clause 4 The FCC certification mark certifies th...

Page 87: ...ic discharge ESD ESD can damage the highly sensitive components in your card ESD damage is most likely to occur as the module is being installed or when cables are connected or disconnected Protect the circuits from ESD damage by wearing a grounding strap that provides a low resistance path to ground Alternatively ground yourself to discharge any built up static charge by touching the outer shell ...

Page 88: ...tion and reference material specific to your ADC card product Data Sheet In addition to a detailed product introduction the data sheet supplies full product specifications Soft Front Panel help system Provides information on the use of the Soft Front Panel IVI Driver reference help system Provides detailed documentation of the IVI NET and IVI C driver API functions as well as information to help y...

Page 89: ...This information is subject to change without notice Acqiris SA 2019 2020 Tuesday June 15 2021 Switzerland www acqiris com ...

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